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Re: [AArch64] Add special case when expanding vcond with arms {-1, -1}, {0, 0}.
- From: Marcus Shawcroft <marcus dot shawcroft at gmail dot com>
- To: James Greenhalgh <james dot greenhalgh at arm dot com>
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, Marcus Shawcroft <marcus dot shawcroft at arm dot com>
- Date: Tue, 30 Apr 2013 18:22:10 +0100
- Subject: Re: [AArch64] Add special case when expanding vcond with arms {-1, -1}, {0, 0}.
- References: <1367334387-22610-1-git-send-email-james dot greenhalgh at arm dot com>
OK
/Marcus
On 30 April 2013 16:06, James Greenhalgh <james.greenhalgh@arm.com> wrote:
>
> If the end goal of a VEC_COND_EXPR is to pick between
> {-1, -1, -1, -1} and {0, 0, 0, 0}
> then we do not need to do a bit select, this is just
> a move of the generated mask to the result operand.
>
> This patch checks for this case, and emits the
> appropriate instructions. This can save us loading the
> two constant masks and performing a bsl.
>
> The midend turns GE_EXPR style tree codes in to VEC_COND_EXPRS,
> so fixing this folding up earlier in the compiler is not helpful.
>
> Regression tested for aarch64-none-elf with no regressions.
>
> OK?
>
> Thanks,
> James
>
> ---
> gcc/
>
> 2013-04-30 James Greenhalgh <james.greenhalgh@arm.com>
>
> * config/aarch64/aarch64-simd.md
> (vcond<mode>_internal): Handle special cases for constant masks.
> (vcond<mode><mode>): Allow nonmemory_operands for outcome vectors.
> (vcondu<mode><mode>): Likewise.
> (vcond<v_cmp_result><mode>): New.