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[PATCH 9/n, i386]: Merge *vec_extractv2di_1_rex64 with base pattern using x64 isa attribute
- From: Uros Bizjak <ubizjak at gmail dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Thu, 28 Mar 2013 19:21:24 +0100
- Subject: [PATCH 9/n, i386]: Merge *vec_extractv2di_1_rex64 with base pattern using x64 isa attribute
Hello!
2013-03-28 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.md (*vec_extract2vdi_1): Merge with
*vec_extractv2di_1_rex64. Use x64 isa attribute.
Tested on x86_64-pc-linux-gnu {,-m32} and committed to mainline SVN.
Uros.
Index: sse.md
===================================================================
--- sse.md (revision 197207)
+++ sse.md (working copy)
@@ -7426,31 +7426,12 @@
[(set (match_dup 0) (match_dup 1))]
"operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));")
-(define_insn "*vec_extractv2di_1_rex64"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,x,r")
- (vec_select:DI
- (match_operand:V2DI 1 "nonimmediate_operand" " x,0,x,o,o")
- (parallel [(const_int 1)])))]
- "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
- "@
- %vmovhps\t{%1, %0|%0, %1}
- psrldq\t{$8, %0|%0, 8}
- vpsrldq\t{$8, %1, %0|%0, %1, 8}
- %vmovq\t{%H1, %0|%0, %H1}
- mov{q}\t{%H1, %0|%0, %H1}"
- [(set_attr "isa" "*,noavx,avx,*,*")
- (set_attr "type" "ssemov,sseishft1,sseishft1,ssemov,imov")
- (set_attr "length_immediate" "*,1,1,*,*")
- (set_attr "memory" "*,none,none,*,*")
- (set_attr "prefix" "maybe_vex,orig,vex,maybe_vex,orig")
- (set_attr "mode" "V2SF,TI,TI,TI,DI")])
-
(define_insn "*vec_extractv2di_1"
- [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,x,x,x")
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,x,x,x,r")
(vec_select:DI
- (match_operand:V2DI 1 "nonimmediate_operand" " x,0,x,o,x,o")
+ (match_operand:V2DI 1 "nonimmediate_operand" " x,0,x,o,x,o,o")
(parallel [(const_int 1)])))]
- "!TARGET_64BIT && TARGET_SSE
+ "(TARGET_64BIT || TARGET_SSE)
&& !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
%vmovhps\t{%1, %0|%0, %1}
@@ -7458,13 +7439,14 @@
vpsrldq\t{$8, %1, %0|%0, %1, 8}
%vmovq\t{%H1, %0|%0, %H1}
movhlps\t{%1, %0|%0, %1}
- movlps\t{%H1, %0|%0, %H1}"
- [(set_attr "isa" "*,sse2_noavx,avx,sse2,noavx,noavx")
- (set_attr "type" "ssemov,sseishft1,sseishft1,ssemov,ssemov,ssemov")
- (set_attr "length_immediate" "*,1,1,*,*,*")
- (set_attr "memory" "*,none,none,*,*,*")
- (set_attr "prefix" "maybe_vex,orig,vex,maybe_vex,orig,orig")
- (set_attr "mode" "V2SF,TI,TI,TI,V4SF,V2SF")])
+ movlps\t{%H1, %0|%0, %H1}
+ mov{q}\t{%H1, %0|%0, %H1}"
+ [(set_attr "isa" "*,sse2_noavx,avx,sse2,noavx,noavx,x64")
+ (set_attr "type" "ssemov,sseishft1,sseishft1,ssemov,ssemov,ssemov,imov")
+ (set_attr "length_immediate" "*,1,1,*,*,*,*")
+ (set_attr "memory" "*,none,none,*,*,*,*")
+ (set_attr "prefix" "maybe_vex,orig,vex,maybe_vex,orig,orig,orig")
+ (set_attr "mode" "V2SF,TI,TI,TI,V4SF,V2SF,DI")])
(define_insn "*vec_dupv4si"
[(set (match_operand:V4SI 0 "register_operand" "=x,x,x")