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RE: RFC: [MIPS] Add an option to disable ldc1/sdc1

Richard Sandiford wrote:
> Chao-Ying Fu <> writes:
> > Hello All,
> >
> >   Once in a while we got reports about programs (ex: 
> WebKit, FireFox)
> > crash due to ldc1/sdc1 unaligned accesses on MIPS targets.  The root
> > cause is that programmers neglect the alignment issue and cast
> > arbitrary pointers to point to double variables.
> >
> >   Although the correct solution is to fix application source code to
> > fulfill alignment requirements, we want to add a GCC option 
> to disable
> > ldc1 and sdc1 (for the testing purpose or for workaround).  
> On 32-bit
> > MIPS targets, GCC generates lwc1 and swc1 when 
> -mno-ldc1-sdc1 is used,
> > so that the memory address can be just 4-byte aligned to avoid
> > ldc1/sdc1 address exceptions.
> Sounds OK to me, given that the impact of the option is so low.

  Thanks a lot for OK!
> Bikeshed time, but I'd prefer the option to be named after the thing
> that we're guaranteeing, rather than an instruction.  E.g. if the
> problem is that doubles might only be 32-bit aligned, we could have
> -mmisaligned-double (better suggestions welcome).
> What about 64-bit targets?  We can sometimes access doubles 
> using GPRs,
> so on 64-bit targets we could end up using LD and SD to 
> access a double
> even when this option disables LDC1 and SDC1.  I think we'd need to
> patch the move patterns as well.
> If you only see the problem on 32-bit targets, then maybe it would be
> better to have an option that prevents instructions that 
> require greater
> than word alignment.  Say (for sake of argument) -mno-superword-align.
> Then it would be:
> #define ISA_HAS_LDC1_SDC1 \
>   (!ISA_MIPS1 && !TARGET_MIPS16 && (TARGET_64BIT || 

  We only got reports about 32-bit MIPS targets.  But similar issues may happen on 64-bit MIPS targets.
Note that these problematic programs can run fine on other architectures that allow 8-byte
load/store instructions from 4-byte aligned addresses.
For a short-term goal, we can use -mon-superword-align (or other option names) to disable
ldc1 and sdc1 on 32-bit MIPS targets where only ldc1 and sdc1 have this 8-byte alignment rule.
Later, we can extend this option to cover 64-bit MIPS targets.




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