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RFC: [MIPS] Add an option to disable ldc1/sdc1
- From: Chao-Ying Fu <Chao-Ying dot Fu at imgtec dot com>
- To: "'gcc-patches at gcc dot gnu dot org'" <gcc-patches at gcc dot gnu dot org>
- Date: Wed, 13 Feb 2013 22:14:26 +0000
- Subject: RFC: [MIPS] Add an option to disable ldc1/sdc1
Once in a while we got reports about programs (ex: WebKit, FireFox)
crash due to ldc1/sdc1 unaligned accesses on MIPS targets. The root cause is that programmers
neglect the alignment issue and cast arbitrary pointers to point to double variables.
Although the correct solution is to fix application source code to fulfill alignment requirements,
we want to add a GCC option to disable ldc1 and sdc1 (for the testing purpose or for workaround).
On 32-bit MIPS targets, GCC generates lwc1 and swc1 when -mno-ldc1-sdc1 is used,
so that the memory address can be just 4-byte aligned to avoid ldc1/sdc1 address exceptions.
Ex: (The proposed patch)
--- mips.opt (revision 196026)
+++ mips.opt (working copy)
@@ -233,6 +233,10 @@
Target Report RejectNegative Mask(MIPS3D)
Use MIPS-3D instructions
+Target Report Var(TARGET_LDC1_SDC1) Init(1)
+Use ldc1 and sdc1 instruction
Target Report Mask(LLSC)
Use ll, sc and sync instructions
--- mips.h (revision 196026)
+++ mips.h (working copy)
@@ -840,8 +840,9 @@
ST Loongson 2E/2F. */
#define ISA_HAS_CONDMOVE (ISA_HAS_FP_CONDMOVE || TARGET_LOONGSON_2EF)
-/* ISA has LDC1 and SDC1. */
-#define ISA_HAS_LDC1_SDC1 (!ISA_MIPS1 && !TARGET_MIPS16)
+/* ISA has LDC1 and SDC1 and they are enabled. */
+#define ISA_HAS_LDC1_SDC1 \
+ (!ISA_MIPS1 && !TARGET_MIPS16 && TARGET_LDC1_SDC1)
/* ISA has the mips4 FP condition code instructions: FP-compare to CC,
branch on CC, and move (both FP and non-FP) on CC. */
Any feedback? Thanks a lot!