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Re: [PATCH] GCC 4.9 powerpc, merge DF/DD moves
- From: David Edelsohn <dje dot gcc at gmail dot com>
- To: Michael Meissner <meissner at linux dot vnet dot ibm dot com>, gcc-patches at gcc dot gnu dot org
- Date: Tue, 5 Feb 2013 13:45:45 -0500
- Subject: Re: [PATCH] GCC 4.9 powerpc, merge DF/DD moves
- References: <20130130204802.GA17728@ibm-tiger.the-meissners.org>
On Wed, Jan 30, 2013 at 3:48 PM, Michael Meissner
> This patch builds upon the patch in:
> It merges the DFmode and DDmode moves into one pattern. In addition, it merges
> the -mmfpgpr code with the normal floating point moves, using a new conditional
> constraint (wg) that only returns FLOAT_REGS for the power6x.
> I have tested this via bootstrap, and there were no regressions. Is patch
> acceptable to check in when the 4.9 tree opens up?
> 2013-01-30 Michael Meissner <email@example.com>
> * config/rs6000/constraints.md (wg constraint): New constraint to
> return FLOAT_REGS if -mmfpgpr (power6x) was used.
> * config/rs6000/rs6000.h (enum r6000_reg_class_enum): Add wg
> * config/rs6000/rs6000.c (rs6000_debug_reg_global): If
> -mdebug=reg, print wg, wl, wx, and wz constraints.
> (rs6000_init_hard_regno_mode_ok): Initialize new constraints.
> Initialize the reload functions for 64-bit binary/decimal floating
> point types.
> (reg_offset_addressing_ok_p): If we are on a power7 or later, use
> LFIWZX and STFIWX to load/store 32-bit decimal types, and don't
> create the buffer on the stack to overcome not having a 32-bit
> load and store.
> (rs6000_emit_move): Likewise.
> (rs6000_secondary_memory_needed_rtx): Likewise.
> (rs6000_alloc_sdmode_stack_slot): Likewise.
> (rs6000_preferred_reload_class): On VSX, we can create SFmode 0.0f
> via xxlxor, just like DFmode 0.0.
> * config/rs6000/dfp.md (movdd): Delete, combine with binary
> floating point moves in rs6000.md. Combine power6x (mfpgpr) moves
> with other moves by using conditional constraits (wg). Use LFIWZX
> and STFIWX for loading SDmode on power7.
> (movdd splitters): Likewise.
> (movdd_hardfloat32): Likewise.
> (movdd_softfloat32): Likewise.
> (movdd_hardfloat64_mfpgpr): Likewise.
> (movdd_hardfloat64): Likewise.
> (movdd_softfloat64): Likewise.
> * config/rs6000/rs6000.md (FMOVE64): New iterators to combine
> 64-bit binary and decimal floating point moves.
> (FMOVE64X): Likewise.
> (movdf): Combine 64-bit binary and decimal floating point moves.
> Combine power6x (mfpgpr) moves with other moves by using
> conditional constraits (wg).
> (mov<mode> for DFmode/DDmode): Likewise.
> (DFmode/DDmode splitters): Likewise.
> (movdf_hardfloat32): Likewise.
> (mov<mode>_hardfloat32 for DFmode/DDmode): Likewise.
> (movdf_softfloat32): Likewise.
> (movdf_hardfloat64_mfpgpr): Likewise.
> (movdf_hardfloat64): Likewise.
> (mov<mode>_hardfloat64 for DFmode/DDmode): Likewise.
> (movdf_softfloat64): Likewise.
> (mov<mode>_softfloat64 for DFmode/DDmode): Likewise.
> (reload_<mode>_load): Move to later in the file so they aren't in
> the middle of the floating point move insns.
> (reload_<mode>_store): Likewise.
> * doc/md.texi (PowerPC and IBM RS6000 constraints): Document wg
This patch is okay when 4.9 tree opens, in combination with the parts
you included in the TF/TD patch.
Again, please confirm that it still works on pre-POWER7 systems.