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RE: [PING Updated]: [PATCH GCC/ARM] Fix problem that hardreg_cprop opportunities are missed on thumb1



> -----Original Message-----
> From: Ramana Radhakrishnan [mailto:ramana.gcc@googlemail.com]
> Sent: Saturday, November 24, 2012 7:20 AM
> To: Bin Cheng
> Cc: gcc-patches@gcc.gnu.org; Ramana Radhakrishnan; Richard Earnshaw;
Richard
> Sandiford
> Subject: Re: [PING Updated]: [PATCH GCC/ARM] Fix problem that
hardreg_cprop
> opportunities are missed on thumb1
> 
> Ok if no regressions.
>
 
I re-tested it against trunk and committed it as r193841

Thanks.


> Ramana
> 
> On Wed, Oct 10, 2012 at 9:57 AM, Bin Cheng <bin.cheng@arm.com> wrote:
> > Ping^2
> >
> >> -----Original Message-----
> >> From: gcc-patches-owner@gcc.gnu.org
> >> [mailto:gcc-patches-owner@gcc.gnu.org]
> > On
> >> Behalf Of Bin Cheng
> >> Sent: Monday, October 08, 2012 2:36 PM
> >> To: gcc-patches@gcc.gnu.org
> >> Cc: Ramana Radhakrishnan; Richard Earnshaw; 'Richard Sandiford'
> >> Subject: RE: [PING Updated]: [PATCH GCC/ARM] Fix problem that
> > hardreg_cprop
> >> opportunities are missed on thumb1
> >>
> >> Ping.
> >>
> >> > -----Original Message-----
> >> > From: gcc-patches-owner@gcc.gnu.org
> >> > [mailto:gcc-patches-owner@gcc.gnu.org]
> >> On
> >> > Behalf Of Bin Cheng
> >> > Sent: Tuesday, September 25, 2012 4:00 PM
> >> > To: 'Richard Sandiford'
> >> > Cc: Ramana Radhakrishnan; Richard Earnshaw; gcc-patches@gcc.gnu.org
> >> > Subject: RE: [Updated]: [PATCH GCC/ARM] Fix problem that
> >> > hardreg_cprop opportunities are missed on thumb1
> >> >
> >> >
> >> > > -----Original Message-----
> >> > > From: Richard Sandiford [mailto:rdsandiford@googlemail.com]
> >> > > Sent: Wednesday, September 05, 2012 6:09 AM
> >> > > To: Bin Cheng
> >> > > Cc: Ramana Radhakrishnan; 'Eric Botcazou';
> >> > > gcc-patches@gcc.gnu.org
> >> > > Subject: Re: Ping: [PATCH GCC/ARM] Fix problem that hardreg_cprop
> >> > > opportunities are missed on thumb1
> >> >
> >> > > Subtraction of zero isn't canonical rtl though.  Passes after
> >> > > peephole2
> >> > would
> >> > > be well within their rights to simplify the expression back to a
move.
> >> > > From that point of view, making the passes recognise (plus X 0)
> >> > > and (minus
> >> > X 0)
> >> > > as special cases would be inconsistent.
> >> > >
> >> > > Rather than make the Thumb 1 CC usage implicit in the rtl stream,
> >> > > and
> >> > carry
> >> > > the current state around in cfun->machine, it seems like it would
> >> > > be
> >> > better to
> >> > > get md_reorg to rewrite the instructions into a form that makes
> >> > > the use of condition codes explicit.
> >> > >
> >> > > md_reorg also sounds like a better place in the pipeline than
> >> > > peephole2 to
> >> > be
> >> > > doing this kind of transformation, although I admit I have zero
> >> > > evidence
> >> > to
> >> > > back that up...
> >> > >
> >> >
> >> > Hi Richard,
> >> >
> >> > This is the updated patch according to your suggestions. I removed
> >> > the
> >> > peephole2 patterns and introduced function thumb1_reorg to rewrite
> >> > instructions in md_reorg pass.
> >> >
> >> > In addition to missed propagation, this patch also detects
> >> > following
> > case:
> >> >       mov r5, r0
> >> >       str r0, [r4]   <-------miscellaneous irrelevant instructions
> >> >       [cmp r0, 0]    <-------saved
> >> >       bne  .Lxxx
> >> >
> >> > Patch tested on arm-none-eabi/cortex-m0, no regressions introduced.
> >> >
> >> > Is it OK?
> >> >
> >> > Thanks.
> >> >
> >> > 2012-09-25  Bin Cheng  <bin.cheng@arm.com>
> >> >
> >> >     * config/arm/arm.c (thumb1_reorg): New function.
> >> >     (arm_reorg): Call thumb1_reorg.
> >> >     (thumb1_final_prescan_insn): Record src operand in thumb1_cc_op0.
> >> >     * config/arm/arm.md : Remove peephole2 patterns which rewrites
move
> >> >     into subtract of ZERO.
> >>
> >>
> >>




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