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Re: [PATCH] Improve andq $0xffffffff, %reg handling (PR target/53110)

On Thu, Apr 26, 2012 at 5:34 PM, Uros Bizjak <> wrote:
> On Thu, Apr 26, 2012 at 5:28 PM, Jakub Jelinek <> wrote:
>>> > We have a splitter for reg1 = reg2 & 0xffffffff, but only if regnums
>>> > are different. ?But movl %edi, %edi is a cheaper variant of
>>> > andq $0xffffffff, %rdi even with the same register and doesn't clobber
>>> > flags, so this patch attempts to expand it as a zero extension early.
>>> >
>>> > Bootstrapped/regtested on x86_64-linux and i686-linux, ok for trunk?
>>> >
>>> > 2012-04-25 ?Jakub Jelinek ?<>
>>> >
>>> > ? ? ? ?PR target/53110
>>> > ? ? ? ?* config/i386/ (and<mode>3): For andq $0xffffffff, reg
>>> > ? ? ? ?instead expand it as zero extension.
>>> Perhaps we can go all the way and also convert ANDs with $0xff and
>>> $0xffff to relevant zero_extend patterns, like in the referred
>>> splitter.
>> I wasn't sure about 0xffff, on which CPUs it would be a win and on which it
>> would not. ?0xffffffff is a win always.

It is always a win, especially when loading from memory. In the latter
case, no execution units are used, only load (memory read) unit.

> My recent changes to zero_extend expanders should handle this
> automatically, and will undo generation of zero_extend pattern. Please
> see zero_extend<mode>si2_and expander, and how it handles

Attached patch implements this idea. In addition, it fixes the
splitter to not change output mode of zero_extension from HImode and
QImode from DImode to SImode. Although they generate the same
instruction, I think we should better keep original mode here.

2012-04-30  Uros Bizjak  <>

	* config/i386/ (and<mode>3): Expand masking operations with
	0xff, 0xffff or 0xffffffff immediates to corresponding zero_extend RTX.
	(and splitter): Split to DImode zero_extend RTX for DImode operand[0].

Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu
{,-m32} and committed to mainline SVN.


Attachment: p.diff.txt
Description: Text document

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