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[PATCH, i386, middle-end, tessuite] Intel TSX's HLE.
- From: Kirill Yukhin <kirill dot yukhin at gmail dot com>
- To: Uros Bizjak <ubizjak at gmail dot com>, Jakub Jelinek <jakub at redhat dot com>
- Cc: irill Yukhin <kirill dot yukhin at gmail dot com>, Torvald Riegel <triegel at redhat dot com>, Andrew MacLeod <amacleod at redhat dot com>, "H.J. Lu" <hjl dot tools at gmail dot com>, "sergos dot gnu at gmail dot com GCC Patches" <gcc-patches at gcc dot gnu dot org>
- Date: Wed, 18 Apr 2012 13:34:20 +0400
- Subject: [PATCH, i386, middle-end, tessuite] Intel TSX's HLE.
Hello guys,
Since there is no more objections to my RFC, started here [1],
I've implemented rest __atomic builtins in the same way.
It corresponds to Spec, which can be found here [2].
Patch attached.
ChangeLog entry:
2012-04-18 Kirill Yukhin <kirill.yukhin@intel.com>
* builtins.c (get_memmodel): Remove check of upper bound.
(expand_builtin_atomic_compare_exchange): Mask memmodel values.
* config/i386/cpuid.h (bit_HLE): New.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect
HLE support.
* config/i386/i386-protos.h (ix86_generate_hle_prefix): New.
* config/i386/i386-c.c (ix86_target_macros_internal): Set
HLE defines.
(ix86_target_string)<-mhle>: New.
(ix86_option_override_internal)<PTA_HLE>: Ditto.
(ix86_valid_target_attribute_inner_p)<OPT_mhle>: Ditto.
* config/i386/i386.c (ix86_target_string)<OPTION_MASK_ISA_HLE>:
New.
(ix86_valid_target_attribute_inner_p)<OPT_mhle>: Ditto.
(ix86_generate_hle_prefix): Ditto.
* config/i386/i386.h (OPTION_ISA_HLE): Ditto.
(IX86_HLE_ACQUIRE): Ditto.
(IX86_HLE_RELEASE): Ditto.
* config/i386/i386.h (ix86_generate_hle_prefix): Ditto.
* config/i386/i386.opt (mhle): Ditto.
* config/i386/sync.md(atomic_compare_and_swap<mode>): Pass
success model to instruction emitter.
(atomic_fetch_add<mode>): Ditto.
(atomic_exchange<mode>): Ditto.
(atomic_add<mode>): Ditto.
(atomic_sub<mode>): Ditto.
(atomic_<code><mode>): Ditto.
(atomic_compare_and_swap_single<mode>): Define and use argument
for success model.
(atomic_compare_and_swap_double<mode>): Ditto.
* configure.ac: Check if assembler support HLE prefixies.
* configure: Regenerate.
* config.in: Ditto.
testsuite/ChangeLog entry:
2012-04-18 Kirill Yukhin <kirill.yukhin@intel.com>
* gcc.target/i386/hle-cmpxchg-acq-1.c: New.
* gcc.target/i386/hle-cmpxchg-rel-1.c: Ditto.
* gcc.target/i386/hle-add-acq-1.c: Ditto.
* gcc.target/i386/hle-add-rel-1.c: Ditto.
* gcc.target/i386/hle-and-acq-1.c: Ditto.
* gcc.target/i386/hle-and-rel-1.c: Ditto.
* gcc.target/i386/hle-or-acq-1.c: Ditto.
* gcc.target/i386/hle-or-rel-1.c: Ditto.
* gcc.target/i386/hle-sub-acq-1.c: Ditto.
* gcc.target/i386/hle-sub-rel-1.c: Ditto.
* gcc.target/i386/hle-xadd-acq-1.c: Ditto.
* gcc.target/i386/hle-xadd-rel-1.c: Ditto.
* gcc.target/i386/hle-xchg-acq-1.c: Ditto.
* gcc.target/i386/hle-xchg-rel-1.c: Ditto.
* gcc.target/i386/hle-xor-acq-1.c: Ditto.
* gcc.target/i386/hle-xor-rel-1.c: Ditto.
Bootstrap in prgress
Is it OK if bootstrap pass?
[1] - http://gcc.gnu.org/ml/gcc-patches/2012-03/msg00486.html
[2] - http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell/
Thanks, K