This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: CPU_NONE ix86_schedule cpu attribute for -march=nocona


On Tue, Apr 17, 2012 at 7:35 AM, Roman Zhuykov <zhroma@ispras.ru> wrote:
> Hello,
>
> I found the following problem while investigating SMS on x86-64.
> When I run gcc with -march=nocona (on pentium-4 with EM64T extension), all
> latencies in data dependency graph become zeros. The global pointer
> "insn_default_latency" points to insn_default_latency_none, which
> returns zero for any instruction.
> This happens because ix86_schedule cpu attribute is set to CPU_NONE for nocona.
>
> CPU_NONE was introduced by this patch:
> http://gcc.gnu.org/ml/gcc-patches/2008-10/msg00179.html
>
> I think we don't want any scheduler to work with zero latencies on
> such processors (with such -march).
> The following patch fixes the problem for my case with -march=nocona.
> Is it correct to fix the problem like this?
> What to do with 32bit architectures (i386, i486, pentium4, pentium4m,
> prescott) ?
>
> diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
> index af4af7c..38d64e9 100644
> --- a/gcc/config/i386/i386.c
> +++ b/gcc/config/i386/i386.c
> @@ -2989,7 +2989,7 @@ ix86_option_override_internal (bool main_args_p)
> ? ? ? PTA_MMX | PTA_SSE | PTA_SSE2},
> ? ? ?{"prescott", PROCESSOR_NOCONA, CPU_NONE,
> ? ? ? PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3},
> - ? ? ?{"nocona", PROCESSOR_NOCONA, CPU_NONE,
> + ? ? ?{"nocona", PROCESSOR_NOCONA, CPU_GENERIC64,
> ? ? ? PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
> ? ? ? | PTA_CX16 | PTA_NO_SAHF},
> ? ? ?{"core2", PROCESSOR_CORE2_64, CPU_CORE2,
> --

Should we replace all CPU_NONE with CPU_GENERIC32/CPU_GENERIC64?

-- 
H.J.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]