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Re: [PATCH] Atom: Scheduler improvements for better imul placement

On Thu, Apr 12, 2012 at 2:00 PM, Alexander Monakov <> wrote:
>> Can atom execute two IMUL in parallel? ?Or what exactly is the pipeline
>> behavior?
> As I understand from Intel's optimization reference manual, the behavior is as
> follows: if the instruction immediately following IMUL has shorter latency,
> execution is stalled for 4 cycles (which is IMUL's latency); otherwise, a
> 4-or-more cycles latency instruction can be issued after IMUL without a stall.
> In other words, IMUL is pipelined with respect to other long-latency
> instructions, but not to short-latency instructions.

It seems to be modeled in the pipeline description though:

;;; imul insn has 5 cycles latency
(define_reservation "atom-imul-32"
                    "atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4,

;;; imul instruction excludes other non-FP instructions.
(exclusion_set "atom-eu-0, atom-eu-1"
               "atom-imul-1, atom-imul-2, atom-imul-3, atom-imul-4")

at least from my very limited guessing of what the above does.  So, did you
analyze why the scheduler does not properly schedule things for you?


> From reading the patch, I could not understand the link between pipeline
> behavior and what the patch appears to do.
> Hope that helps.
> Alexander

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