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Re: [PATCH][ARM] Improve 64-bit shifts (non-NEON)
- From: Steven Bosscher <stevenb dot gcc at gmail dot com>
- To: Ramana Radhakrishnan <ramana dot radhakrishnan at linaro dot org>
- Cc: Andrew Stubbs <ams at codesourcery dot com>, Richard Earnshaw <rearnsha at arm dot com>, "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>, "patches at linaro dot org" <patches at linaro dot org>
- Date: Tue, 7 Feb 2012 23:33:53 +0100
- Subject: Re: [PATCH][ARM] Improve 64-bit shifts (non-NEON)
- References: <4F22CBB2.email@example.com> <4F26B687.firstname.lastname@example.org> <4F27FAC0.email@example.com> <CACUk7=VFbmkQOTo3ZXA2FMyt14zhiAonArBghFhBrBdvBQGvHg@mail.gmail.com>
On Tue, Feb 7, 2012 at 11:19 PM, Ramana Radhakrishnan
> Hi Andrew
> I find it interesting that cond_exec's in this form survive all the
> way till reload and "work". ?AFAIK we could never have cond_exec's
> before reload .
There is nothing wrong per-se with cond_execs before reload, as long
as you don't have to reload a predicate pseudo-reg. For ia64, with its
(IIRC) 64 predicate registers, it was not practical, or even possible,
to assign the predicate registers to hard regs during expand.
AFAIU this isn't an issue on ARM because there is just one condition