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Hello, The testcase attached causes ICE when compiling with -fmodulo-sched-allow-regmoves on ARM due to reg-moves created for the definition of mode MODE_CC. The following is a snippet from the ddg of the definition and use of vfpcc which triggers the creation of the reg-move: Node num: 1 (insn 151 77 152 6 (set (reg:CCFP 127 vfpcc) (compare:CCFP (reg:SF 202 [ MEM[base: D.5306_32, offset: 0B] ]) (reg:SF 183 [ D.5284 ]))) test_new.c:8 694 {*cmpsf_vfp} (expr_list:REG_DEAD (reg:SF 202 [ MEM[base: D.5306_32, offset: 0B] ]) (nil))) OUT ARCS: [151 -(T,4,0)-> 152] IN ARCS: [77 -(T,3,0)-> 151] Node num: 2 (insn 152 151 120 6 (set (reg:CCFP 24 cc) (reg:CCFP 127 vfpcc)) test_new.c:8 689 {*movcc_vfp} (expr_list:REG_DEAD (reg:CCFP 127 vfpcc) (nil))) OUT ARCS: [152 -(O,0,0)-> 144] [152 -(T,0,0)-> 120] IN ARCS: [145 -(A,0,1)-> 152] [151 -(T,4,0)-> 152] The attached patch prevents the creation of reg-moves for definitions with MODE_CC and thus solves this ICE. Currently testing and bootstrap on ppc64-redhat-linux, enabling SMS on loops with SC 1. OK for 4.7 once testing completes? Thanks, Revital Changelog: gcc/ * ddg.c (def_has_ccmode_p): New function. (add_cross_iteration_register_deps): Call it. testsuite/ * gcc.dg/sms-11.c: New file.
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patch_fix_ddg_20_12.txt
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