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Re: [PATCH] Fix up VEC_INTERLEAVE_*_EXPR folding and expansion for big endian (PR tree-optimization/51074)
On 12/01/2011 03:21 AM, Richard Guenther wrote:
> Yes, sorry - I'm recovering from a 3 week e-mail lag ;) I agree
> using VEC_PERM_EXPR would be best - but that would also affect
> backend patterns. Can we have a middle-ground that leaves those
> untouched? We're still in stage 3, so fixing the bug with using
> VEC_PERM_EXPR sounds appealing to me ;)
If we agree that we want to fix this with vec_perm_expr, then we need a relatively minor patch to the vectorizer, and cleanups in the targets.
In particular, powerpc, spu, and ia64 will need to recognize various constant permutations so that they can continue using the specialized instructions for interleave. This shouldn't be particularly difficult; a few testcases added to make sure we don't regress to full permutation wouldn't be amiss.
The x86 port is the only one that really does aggressive constant permutation pattern recognition atm. That is, of course, because the ISA support for permutation there is all over the map and we had no choice.
I've already zapped the target patterns that expanded interleave/even_odd back into a permuation operation.
If we think this is ok for stage3, we can certainly give it a whack. I'll take care of the backends if Jakub takes care of the vectorizer?
r~