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Here is the correct file 1-ldrdstrd.patch. Sorry. -- Greta > -----Original Message----- > From: Greta Yorsh [mailto:Greta.Yorsh@arm.com] > Sent: 07 November 2011 11:45 > To: gcc-patches@gcc.gnu.org > Cc: nickc@redhat.com; Richard Earnshaw; paul@codesourcery.com; Ramana > Radhakrishnan; Carrot@google.com > Subject: [PATCH,ARM][1/6] Merge LDR/STR into LDRD/STRD with -O2 in > Thumb > > Generate LDRD/STRD in Thumb mode with -O2 for CPUs that set > "prefer_ldrd_strd" tune flag. This flag is currently set only for > cortex-a15. > > The patch consists of > * define_insn for LDRD/STRD, > * peephole2 patterns that merge LDR/STR into LDRD/STRD, > * peephole2 patterns that attempt to rename and reorder registers to > enable > LDRD/STRD, and > * fix existing tests to accept LDRD/STRD in addition to LDM/STM. > > The new patterns and peephole optimizations are placed in a new file, > ldrdstrd0.md, which is included in arm.md before ldmstm.md, and thus > when > LDRD/STRD cannot be generated, LDM/STM may still be generated. The file > ldrdstrd0.md is automatically generated (see patch no. 3 in the > series). > > This patch depends on the patch for prefer_ldrd_strd tune flag, > submitted > here: > http://gcc.gnu.org/ml/gcc-patches/2011-10/msg00858.html > > This patch is inspired by the following: > * Existing LDM/STM patterns and peephole optimizations. > * Sameera's patches for prolog/epilog using LDRD/STRD: > http://gcc.gnu.org/ml/gcc-patches/2011-10/msg00856.html > * Carrot's patch for merging LDR/STR into LDRD/STRD, which was > unfortunately > breaking the build and had to be reverted. In particular, test files > gcc.target/arm/pr45335*.c are from Carrot's patch. > http://gcc.gnu.org/ml/gcc-patches/2011-06/msg01250.html > > > The patterns introduced by this patch use a new constraint, defined as > follows: > +(define_register_constraint "q" "TARGET_ARM && TARGET_LDRD ? CORE_REGS > : > GENERAL_REGS" > + "@internal In ARM state with LDRD support, core registers, otherwise > general registers.") > > Register class CORE_REGS consists of registers r0-r15. Register class > GENERAL_REGS consists of registers r0-12,r14,r15. The difference is > that > GENERAL_REGS class does not contain r13, which is the stack pointer > register > (SP). Therefore, in Thumb mode, "q" constraint is equivalent to "r" > (which > stands for GENERAL_REGS), and in ARM mode, "q" constraint also allows > SP. > > The "q" constraint is used in patterns for LDRD/STRD. In Thumb mode, SP > is > not allowed as the destination register in LDRD/STRD. In ARM mode only, > the > pair of registers IP and SP is allowed in LDRD/STRD. The "q" constraint > allows us to treat these two cases uniformly in the patterns, without > missing opportunities for generating LDRD/STRD. It is not common for SP > to > be written to memory or read from memory, but it happens for example in > some > regression tests for builtins that create call chains. > > > gcc/ChangeLog > > 2011-10-28 Greta Yorsh <Greta.Yorsh@arm.com> > > * config/arm/arm.md: Include ldrdstrd.md. > * config/arm/ldrdstrd0.md: New file. Adds define_insn and > peepholes > for Thumb mode. > * config/arm/predicates.md (arm_hard_core_register_operand): > New > predicate. > * config/arm/constraints.md (q): New constraint. > * config/arm/arm-protos.h (bad_operands_ldrd_strd): New > prototype. > (gen_operands_ldrd_strd) New prototype. > (gen_operands_const_strd) New prototype. > * config/arm/arm.c (bad_offset_ldrd_strd): New function. > (bad_operands_ldrd_strd): New function. > (bad_mem_for_ldrd_strd): New function. > (gen_operands_ldrd_strd): New function. > (gen_operands_const_strd): New function. > (find_free_regs_for_arm_const_strd): New function. > > gcc/testsuite/ChangeLog > > 2011-10-28 Carrot Wei <Carrot@google.com> > Greta Yorsh <Greta.Yorsh@arm.com> > > PR target/45335 > * gcc.target/arm/pr45335.c: New file. > * gcc.target/arm/pr45335-2.c: New file. > * gcc.target/arm/pr45335-3.c: New file. > > * gcc.target/arm/pr40457-3.c: Update to accept new compiler > output. > * gcc.target/arm/pr40457-2.c: Likewise. > * gcc.target/arm/pr40457-1.c: Likewise.
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