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Re: [ARM] Fix PR49641
- From: Richard Earnshaw <rearnsha at arm dot com>
- To: Bernd Schmidt <bernds at codesourcery dot com>
- Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>, Ramana Radhakrishnan <Ramana dot Radhakrishnan at arm dot com>
- Date: Mon, 17 Oct 2011 13:54:30 +0100
- Subject: Re: [ARM] Fix PR49641
- References: <4E1610ED.2070108@codesourcery.com> <4E1DA5C4.60806@arm.com> <4E983996.4030908@codesourcery.com>
On 14/10/11 14:31, Bernd Schmidt wrote:
> On 07/13/11 16:03, Richard Earnshaw wrote:
>>> * config/arm/arm.c (store_multiple_sequence): Avoid cases where
>>> the base reg is stored iff compiling for Thumb1.
>>>
>>> * gcc.target/arm/pr49641.c: New test.
>
> Ping. Richard, you replied to the mail but didn't comment on the patch.
>
>
> Bernd
>
Sorry, I thought I'd made it clear that I don't think the compiler
should ever use STM with write-back if the base register is in the
stored list. We must certainly never do it if the base register is not
the first register in the list as this has always been unpredictable.
BTW, this is not Thumb1 specific, it applies at all times.
So, no the patch is not OK as it stands.
R.