This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
[PATCH] Fix VIS3 assembler check and conditionalize testsuite on VIS3 support.
- From: David Miller <davem at davemloft dot net>
- To: gcc-patches at gcc dot gnu dot org
- Cc: ro at CeBiTec dot Uni-Bielefeld dot DE
- Date: Fri, 07 Oct 2011 13:25:18 -0400 (EDT)
- Subject: [PATCH] Fix VIS3 assembler check and conditionalize testsuite on VIS3 support.
Committed to trunk.
gcc/
PR 50655
* configure.ac: Add .register directives to VIS3 test.
* configure: Regenerate.
gcc/testsuite/
PR 50655
* gcc.target/sparc/sparc.exp: Add vis3 target test.
* gcc.target/sparc/cmask.c: Use it.
* gcc.target/sparc/fhalve.c: Likewise.
* gcc.target/sparc/fnegop.c: Likewise.
* gcc.target/sparc/fpadds.c: Likewise.
* gcc.target/sparc/fshift.c: Likewise.
* gcc.target/sparc/fucmp.c: Likewise.
* gcc.target/sparc/lzd.c: Likewise.
* gcc.target/sparc/vis3misc.c: Likewise.
* gcc.target/sparc/xmul.c: Likewise.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@179667 138bc75d-0d04-0410-961f-82ee72b054a4
---
gcc/ChangeLog | 6 ++++++
gcc/configure | 2 ++
gcc/configure.ac | 2 ++
gcc/testsuite/ChangeLog | 16 +++++++++++++++-
gcc/testsuite/gcc.target/sparc/cmask.c | 2 +-
gcc/testsuite/gcc.target/sparc/fhalve.c | 2 +-
gcc/testsuite/gcc.target/sparc/fnegop.c | 2 +-
gcc/testsuite/gcc.target/sparc/fpadds.c | 2 +-
gcc/testsuite/gcc.target/sparc/fshift.c | 2 +-
gcc/testsuite/gcc.target/sparc/fucmp.c | 2 +-
gcc/testsuite/gcc.target/sparc/lzd.c | 2 +-
gcc/testsuite/gcc.target/sparc/sparc.exp | 11 +++++++++++
gcc/testsuite/gcc.target/sparc/vis3misc.c | 2 +-
gcc/testsuite/gcc.target/sparc/xmul.c | 2 +-
14 files changed, 45 insertions(+), 10 deletions(-)
diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index f840e46..573ce6e 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2011-10-07 David S. Miller <davem@davemloft.net>
+
+ PR 50655
+ * configure.ac: Add .register directives to VIS3 test.
+ * configure: Regenerate.
+
2011-10-07 Richard Henderson <rth@redhat.com>
* config.gcc (x86_64-*): Add core-avx-i, core-avx2 for with_cpu.
diff --git a/gcc/configure b/gcc/configure
index ac32705..cb55dda 100755
--- a/gcc/configure
+++ b/gcc/configure
@@ -24060,6 +24060,8 @@ else
gcc_cv_as_sparc_fmaf=no
if test x$gcc_cv_as != x; then
$as_echo '.text
+ .register %g2, #scratch
+ .register %g3, #scratch
.align 4
fmaddd %f0, %f2, %f4, %f6
addxccc %g1, %g2, %g3
diff --git a/gcc/configure.ac b/gcc/configure.ac
index ed52c91..a7b94e6 100644
--- a/gcc/configure.ac
+++ b/gcc/configure.ac
@@ -3491,6 +3491,8 @@ foo:
gcc_cv_as_sparc_fmaf,,
[-xarch=v9d],
[.text
+ .register %g2, #scratch
+ .register %g3, #scratch
.align 4
fmaddd %f0, %f2, %f4, %f6
addxccc %g1, %g2, %g3
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index aff35a6..ea79b60 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,17 @@
+2011-10-07 David S. Miller <davem@davemloft.net>
+
+ PR 50655
+ * gcc.target/sparc/sparc.exp: Add vis3 target test.
+ * gcc.target/sparc/cmask.c: Use it.
+ * gcc.target/sparc/fhalve.c: Likewise.
+ * gcc.target/sparc/fnegop.c: Likewise.
+ * gcc.target/sparc/fpadds.c: Likewise.
+ * gcc.target/sparc/fshift.c: Likewise.
+ * gcc.target/sparc/fucmp.c: Likewise.
+ * gcc.target/sparc/lzd.c: Likewise.
+ * gcc.target/sparc/vis3misc.c: Likewise.
+ * gcc.target/sparc/xmul.c: Likewise.
+
2011-10-07 Richard Henderson <rth@redhat.com>
* gcc.target/i386/avx256-unaligned-load-2.c: Tweek vinsert pattern
@@ -17,7 +31,7 @@
2011-10-06 Joern Rennecke <joern.rennecke@embecosm.com>
* gcc.dg/pr47276.c (ASMNAME, ASMNAME2, STRING): Define.
- (__EI___vsyslog_chk, __EI_syslog, __EI_vsyslog): Use ASMNAME.
+ (__EI___vsyslog_chk, __EI_syslog, __EI_vsyslog): Use ASMNAME.
(syslog, vsyslog, __vsyslog_chk): Likewise.
* gcc.dg/lto/20081222_1.c (ASMNAME, ASMNAME2, STRING): Define.
diff --git a/gcc/testsuite/gcc.target/sparc/cmask.c b/gcc/testsuite/gcc.target/sparc/cmask.c
index b3168ec..989274c 100644
--- a/gcc/testsuite/gcc.target/sparc/cmask.c
+++ b/gcc/testsuite/gcc.target/sparc/cmask.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
void test_cm8 (long x)
diff --git a/gcc/testsuite/gcc.target/sparc/fhalve.c b/gcc/testsuite/gcc.target/sparc/fhalve.c
index 340b936..737fc71 100644
--- a/gcc/testsuite/gcc.target/sparc/fhalve.c
+++ b/gcc/testsuite/gcc.target/sparc/fhalve.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
float test_fhadds (float x, float y)
diff --git a/gcc/testsuite/gcc.target/sparc/fnegop.c b/gcc/testsuite/gcc.target/sparc/fnegop.c
index 25f8c19..3e3e72c 100644
--- a/gcc/testsuite/gcc.target/sparc/fnegop.c
+++ b/gcc/testsuite/gcc.target/sparc/fnegop.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-O2 -mcpu=niagara3 -mvis" } */
float test_fnadds(float x, float y)
diff --git a/gcc/testsuite/gcc.target/sparc/fpadds.c b/gcc/testsuite/gcc.target/sparc/fpadds.c
index d0704e0..f55cb05 100644
--- a/gcc/testsuite/gcc.target/sparc/fpadds.c
+++ b/gcc/testsuite/gcc.target/sparc/fpadds.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
typedef int __v2si __attribute__((vector_size(8)));
typedef int __v1si __attribute__((vector_size(4)));
diff --git a/gcc/testsuite/gcc.target/sparc/fshift.c b/gcc/testsuite/gcc.target/sparc/fshift.c
index a12df04..6adbed6 100644
--- a/gcc/testsuite/gcc.target/sparc/fshift.c
+++ b/gcc/testsuite/gcc.target/sparc/fshift.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
typedef int __v2si __attribute__((vector_size(8)));
typedef short __v4hi __attribute__((vector_size(8)));
diff --git a/gcc/testsuite/gcc.target/sparc/fucmp.c b/gcc/testsuite/gcc.target/sparc/fucmp.c
index 7f291c3..4e7ecad 100644
--- a/gcc/testsuite/gcc.target/sparc/fucmp.c
+++ b/gcc/testsuite/gcc.target/sparc/fucmp.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
typedef unsigned char vec8 __attribute__((vector_size(8)));
diff --git a/gcc/testsuite/gcc.target/sparc/lzd.c b/gcc/testsuite/gcc.target/sparc/lzd.c
index a897829..5ffaf56 100644
--- a/gcc/testsuite/gcc.target/sparc/lzd.c
+++ b/gcc/testsuite/gcc.target/sparc/lzd.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3" } */
int test_clz(int a)
{
diff --git a/gcc/testsuite/gcc.target/sparc/sparc.exp b/gcc/testsuite/gcc.target/sparc/sparc.exp
index 9658d08..51c9c16 100644
--- a/gcc/testsuite/gcc.target/sparc/sparc.exp
+++ b/gcc/testsuite/gcc.target/sparc/sparc.exp
@@ -24,6 +24,17 @@ if ![istarget sparc*-*-*] then {
# Load support procs.
load_lib gcc-dg.exp
+# Return 1 if vis3 instructions can be compiled.
+proc check_effective_target_vis3 { } {
+ return [check_no_compiler_messages vis3 object {
+ long long
+ _vis3_fpadd64 (long long __X, long long __Y)
+ {
+ return __builtin_vis_fpadd64 (__X, __Y);
+ }
+ } "-mcpu=niagara3 -mvis" ]
+}
+
# If a testcase doesn't have special options, use these.
global DEFAULT_CFLAGS
if ![info exists DEFAULT_CFLAGS] then {
diff --git a/gcc/testsuite/gcc.target/sparc/vis3misc.c b/gcc/testsuite/gcc.target/sparc/vis3misc.c
index 8a9535e..e3ef49e 100644
--- a/gcc/testsuite/gcc.target/sparc/vis3misc.c
+++ b/gcc/testsuite/gcc.target/sparc/vis3misc.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
typedef int __v2si __attribute__((vector_size(8)));
typedef short __v4hi __attribute__((vector_size(8)));
diff --git a/gcc/testsuite/gcc.target/sparc/xmul.c b/gcc/testsuite/gcc.target/sparc/xmul.c
index ce80e6c..5d249d0 100644
--- a/gcc/testsuite/gcc.target/sparc/xmul.c
+++ b/gcc/testsuite/gcc.target/sparc/xmul.c
@@ -1,4 +1,4 @@
-/* { dg-do compile } */
+/* { dg-do compile { target { vis3 } } } */
/* { dg-options "-mcpu=niagara3 -mvis" } */
typedef long long int64_t;
--
1.7.6.401.g6a319