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[Committed] S/390: Add umulditi pattern
- From: "Andreas Krebbel" <krebbel at linux dot vnet dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 7 Oct 2011 08:54:40 +0200
- Subject: [Committed] S/390: Add umulditi pattern
Hi,
this patch adds support for the 64x64->128 bit unsigned multiplication
to the s390 backend. We always the instruction but for some reason
forgot to add a pattern :(
Thanks to Torbjorn Granlund for the pointer!
Committed to mainline after testing on s390 and s390x.
Bye,
-Andreas-
2011-10-07 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* config/s390/s390.md (DWH, dwh): New mode macros.
("umulsidi3"): Extend to support "umulditi3" as well.
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig
--- gcc/config/s390/s390.md
***************
*** 367,372 ****
--- 367,376 ----
(define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")])
(define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")])
+ ;; Used by the umul pattern to express modes having half the size.
+ (define_mode_attr DWH [(TI "DI") (DI "SI")])
+ (define_mode_attr dwh [(TI "di") (DI "si")])
+
;; This mode iterator allows the QI and HI patterns to be defined from
;; the same template.
(define_mode_iterator HQI [HI QI])
***************
*** 5456,5476 ****
(set_attr "cpu_facility" "*,*,z10")])
;
! ; umulsidi3 instruction pattern(s).
;
! (define_insn "umulsidi3"
! [(set (match_operand:DI 0 "register_operand" "=d,d")
! (mult:DI (zero_extend:DI
! (match_operand:SI 1 "register_operand" "%0,0"))
! (zero_extend:DI
! (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))]
! "!TARGET_ZARCH && TARGET_CPU_ZARCH"
"@
! mlr\t%0,%2
! ml\t%0,%2"
[(set_attr "op_type" "RRE,RXY")
! (set_attr "type" "imulsi")])
;
; mul(tf|df|sf|td|dd)3 instruction pattern(s).
--- 5460,5481 ----
(set_attr "cpu_facility" "*,*,z10")])
;
! ; umul instruction pattern(s).
;
! ; mlr, ml, mlgr, mlg
! (define_insn "umul<dwh><mode>3"
! [(set (match_operand:DW 0 "register_operand" "=d, d")
! (mult:DW (zero_extend:DW
! (match_operand:<DWH> 1 "register_operand" "%0, 0"))
! (zero_extend:DW
! (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))]
! "TARGET_CPU_ZARCH"
"@
! ml<tg>r\t%0,%2
! ml<tg>\t%0,%2"
[(set_attr "op_type" "RRE,RXY")
! (set_attr "type" "imul<dwh>")])
;
; mul(tf|df|sf|td|dd)3 instruction pattern(s).