This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [Patch,AVR]: PR49687 (better widening 32-bit mul)
On 07/27/2011 08:57 AM, Georg-Johann Lay wrote:
>> > You'll probably end up with quite a few register classes
>> > out of this, but hopefully reload can do a better job than
>> > you can manually...
> Agreed.
>
> insns that will benefit are insns with two input operands that
> commute, i.e. mulsi3, umulhisi3, mulhisi3, mulhi3.
>
> Maybe even other 2-input insns could benefit because there's no
> predetermined order in which the moves are accomplished; e.g.
> moving R24 before R22 in udivmodqi4. I don't know if register
> allocator is smart enough to swap the assignments if that is
> better.
>
> Moreover, it would reduce the number of insns resp. split
> patterns and help cleanup md.
>
> I'd prefer to do that work in a separate patch. The current patch
> behaves the same as the old code, so it's not a performance
> regression of the current patch.
Fair enough.
I didn't review the asm code, but the rest of the patch look ok to me.
r~