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[PATCH, i386]: Expand insv pattern to pinsr{q,w,d,q} insn

From: Uros Bizjak <ubizjak at gmail dot com>
To: gcc-patches at gcc dot gnu dot org
Date: Wed, 20 Apr 2011 21:54:28 +0200
Subject: [PATCH, i386]: Expand insv pattern to pinsr{q,w,d,q} insn

Hello!

Attached patch enhances the fix for PR target/48678 to generate
pinsr{q,w,d,q} insn when value is inserted into vector register.

2011-04-20  Uros Bizjak  <ubizjak@gmail.com>

	PR target/48678
	* config/i386/i386.md (insv): Change operand 0 constraint to
	"register_operand".  Change operand 1 and 2 constraint to
	"const_int_operand".  Expand to pinsr{b,w,d,q} * when appropriate.
	* config/i386/sse.md (sse4_1_pinsrb): Export.
	(sse2_pinsrw): Ditto.
	(sse4_1_pinsrd): Ditto.
	(sse4_1_pinsrq): Ditto.
	* config/i386/i386-protos.h (ix86_expand_pinsr): Add prototype.
	* config/i386/i386.c (ix86_expand_pinsr): New.

testsuite/ChangeLog:

2011-04-20  Uros Bizjak  <ubizjak@gmail.com>

	PR target/48678
	* gcc.target/i386/sse2-pinsrw.c: New test.
	* gcc.target/i386/avx-vpinsrw.c: Ditto.
	* gcc.target/i386/sse4_1-insvqi.c: Ditto.
	* gcc.target/i386/sse2-insvhi.c: Ditto.
	* gcc.target/i386/sse4_1-insvsi.c: Ditto.
	* gcc.target/i386/sse4_1-insvdi.c: Ditto.

Patch was bootstrapped and regression tested on x86_64-pc-linux-gnu
{-m32}.  Committed to mainline SVN.

Uros.

Attachment: p.diff.txt
Description: Text document

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