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Re: [PATCH] Fix PR 46521 and 46522 (remnants of PR45352)
- From: Andrey Belevantsev <abel at ispras dot ru>
- To: Vladimir Makarov <vmakarov at redhat dot com>
- Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Fri, 24 Dec 2010 12:45:58 +0300
- Subject: Re: [PATCH] Fix PR 46521 and 46522 (remnants of PR45352)
- References: <4CC13E91.2000800@ispras.ru> <4CD1530D.6040006@ispras.ru> <4CD46884.8010003@redhat.com> <4D10CE93.9090300@ispras.ru> <4D10E483.90205@redhat.com>
On 12/21/2010 10:58 AM, Andrey Belevantsev wrote:
2010-12-21 Andrey Belevantsev <abel@ispras.ru>
PR rtl-optimization/45352
PR rtl-optimization/46521
PR rtl-optimization/46522
* sel-sched.c (reset_sched_cycles_in_current_ebb): Recheck the DFA state
on the last iteration of the advancing loop.
(sel_sched_region_1): Propagate the rescheduling bit to the next block
also for empty blocks.
Sigh, I have overlooked that we also need to recheck the state when we have
reached the issue_rate limit (as we agreed on earlier this year), not only
when we have a data dependency stall. So the above amendment to the patch
is needed, bootstrapped and tested on x86-64 with selective scheduler
enabled. Ok for trunk and branches?
Andrey
2010-12-21 Andrey Belevantsev <abel@ispras.ru>
PR rtl-optimization/45352
* sel-sched.c (reset_sched_cycles_in_current_ebb): Also recheck the DFA state
in the advancing loop when we have issued issue_rate insns.
gcc/testsuite:
2010-12-21 Andrey Belevantsev <abel@ispras.ru>
PR rtl-optimization/45352
gcc.dg/pr45352-3.c: New.
Index: testsuite/gcc.dg/pr45352-3.c
===================================================================
*** testsuite/gcc.dg/pr45352-3.c (revision 0)
--- testsuite/gcc.dg/pr45352-3.c (revision 0)
***************
*** 0 ****
--- 1,16 ----
+ /* { dg-do compile { target powerpc*-*-* ia64-*-* x86_64-*-* } } */
+ /* { dg-options "-O -fprofile-generate -fgcse -fno-gcse-lm -fgcse-sm -fno-ivopts -fno-tree-loop-im -ftree-pre -funroll-loops -fno-web -fschedule-insns2 -fselective-scheduling2 -fsel-sched-pipelining" } */
+
+ extern volatile float f[];
+
+ void foo (void)
+ {
+ int i;
+ for (i = 0; i < 100; i++)
+ f[i] = 0;
+ for (i = 0; i < 100; i++)
+ f[i] = 0;
+ for (i = 0; i < 100; i++)
+ if (f[i])
+ __builtin_abort ();
+ }
Index: sel-sched.c
===================================================================
*** sel-sched.c (revision 168224)
--- sel-sched.c (working copy)
*************** reset_sched_cycles_in_current_ebb (void)
*** 6990,6996 ****
{
int cost, haifa_cost;
int sort_p;
! bool asm_p, real_insn, after_stall;
int clock;
if (!INSN_P (insn))
--- 6990,6996 ----
{
int cost, haifa_cost;
int sort_p;
! bool asm_p, real_insn, after_stall, all_issued;
int clock;
if (!INSN_P (insn))
*************** reset_sched_cycles_in_current_ebb (void)
*** 7026,7033 ****
haifa_cost = cost;
after_stall = 1;
}
! if (haifa_cost == 0
! && issued_insns == issue_rate)
haifa_cost = 1;
if (haifa_cost > 0)
{
--- 7026,7033 ----
haifa_cost = cost;
after_stall = 1;
}
! all_issued = issued_insns == issue_rate;
! if (haifa_cost == 0 && all_issued)
haifa_cost = 1;
if (haifa_cost > 0)
{
*************** reset_sched_cycles_in_current_ebb (void)
*** 7055,7065 ****
break;
/* When the data dependency stall is longer than the DFA stall,
! it could be that after the longer stall the insn will again
become unavailable to the DFA restrictions. Looks strange
but happens e.g. on x86-64. So recheck DFA on the last
iteration. */
! if (after_stall
&& real_insn
&& haifa_cost == 0)
haifa_cost = estimate_insn_cost (insn, curr_state);
--- 7055,7066 ----
break;
/* When the data dependency stall is longer than the DFA stall,
! and when we have issued exactly issue_rate insns and stalled,
! it could be that after this longer stall the insn will again
become unavailable to the DFA restrictions. Looks strange
but happens e.g. on x86-64. So recheck DFA on the last
iteration. */
! if ((after_stall || all_issued)
&& real_insn
&& haifa_cost == 0)
haifa_cost = estimate_insn_cost (insn, curr_state);