Re: [patch][ARM] Don't generate redundant zero_extend before smlabb

[Richard Sandiford <richard dot sandiford at linaro dot org>]

Andrew Stubbs <ams@codesourcery.com> writes:
> The attached patch adjusts the ARM machine description to prevent GCC 
> emitting redundant zero-extends before 16-bit->32-bit multiply and 
> accumulate operations.
>
> The problem is that maddhisi4 pattern has the operands of plus swapped, 
> with respect to the (de facto?) canonical form always returned by 
> combine_simplify_rtx. This means that recog does not match the pattern, 
> and the zero-extends are not optimized away.
>
> The patch simply swaps the order of the operands. maddhidi4 appears to 
> have a similar problem, so I've corrected it there also.
>
> Test case:
>
> int footrunc (int x, int a, int b)
> {
>       return x + (short) a * (short) b;
> }
>
> Before, compiled with "-O2":
>
>           mov     ip, r1, asl #16
>           mov     r3, r2, asl #16
>           mov     r1, ip, lsr #16
>           mov     r2, r3, lsr #16
>           smlabb  r0, r2, r1, r0
>           bx      lr
>
> (On armv7a/thumb2 the code uses uxth, but the problem is the same.)
>
> After:
>           smlabb  r0, r1, r2, r0
>           bx      lr
>
> OK for commit, after stage 1 opens again?

Could this go in during stage 3?  Like you say, the current maddhisi4
expander (which is known to optabs) generates "noncanonical" rtx.
That seems like a bug.

Richard