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[PATCH, ARM] Fix PR46883, ICE at reload
- From: Chung-Lin Tang <cltang at codesourcery dot com>
- To: gcc-patches <gcc-patches at gcc dot gnu dot org>
- Date: Tue, 14 Dec 2010 22:05:23 +0800
- Subject: [PATCH, ARM] Fix PR46883, ICE at reload
Hi, this patch tries to fix PR46883, where reload ICEs at an
unrecognized insn.
The failing insn is produced during split1. The "register_operand"
predicate allows (subreg (mem)) before reload, which allows the
zero_extend_qisi2 register splitter to hook on and create (subreg:QI
(mem:HI (post_inc ...))), which causes reload to ICE (in two different
places, depending on -O1 or -O2).
While reload may need further work later, this patch changes the
predicates above to use the ARM backend's "s_register_operand", which
matches only regs/subregs of regs. This resolves the ICE, and seems to
more closely match the original intention of the splitters.
The PR testcase triggers the ICE due to the QI/SI splitter, but I have
fixed the HI/SI splitter too, as it seems to be analogous.
Tested without regressions. Ok to commit?
Thanks,
Chung-Lin
2010-12-14 Chung-Lin Tang <cltang@codesourcery.com>
PR target/46883
* config/arm/arm.md
(zero_extendhisi2 for register input splitter): Change
"register_operand" to "s_register_operand".
(zero_extendqisi2 for register input splitter): Same.
Attachment:
qihi-split.diff
Description: Text document