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Re: [patch, CSE] Bit-field insertion optimization
- From: Jeff Law <law at redhat dot com>
- To: Andrew Stubbs <ams at codesourcery dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Fri, 10 Dec 2010 09:00:33 -0700
- Subject: Re: [patch, CSE] Bit-field insertion optimization
- References: <4D010797.60004@codesourcery.com>
On 12/09/10 09:45, Andrew Stubbs wrote:
The attached patch fixes a bug in which constant assignments to bit
fields are improperly optimized. I'm seeing this on ARM, but I imagine
it affects other targets similarly.
The first problem is that CSE cannot determine that the result is
constant because the auto-variable is implicitly initialized. I have
solved this by moving up the init-regs pass to before cse2. It might
be better to move it before cse1, but that's a bigger change, so I
wasn't sure?
If this change ends up being made, I would strongly recommend a comment
about why the change was made be placed in passes.c.
I would hazard a guess that the pass was placed late in the pipeline
because there wasn't any value seen in running it prior to combine. The
only thing I'd be concerned about would be introducing useless
initializations if we move the pass earlier since fewer optimizers would
have been run and thus more unexecutable paths are still in the CFG. It
would be particularly interesting to run some benchmarks with only this
change and see how codesize is affected.
The second problem is that the pattern match for ZERO_EXTRACT requires
that the operand is an immediate constant, which is never the case on
ARM (and presumably is only the case with a limited range of inputs
even on other targets). I have added code to detect known-constant
input registers.
This seems fairly reasonable.
I believe the preferred method for queuing pending patches is to open
a bug for failure to optimize, attach the patches & testcase to that
bug. Then make the GCC 4.7 pending patches meta-bug depend on the
failure to optimize bug.
Jeff