PATCH: Turn on unaligned SSE load/store for Core i7

["H.J. Lu" <hongjiu dot lu at intel dot com>]

Hi,

This patch turns on unaligned SSE load/store for Core i7.  It improves
SPEC CPU 2000/2006 FP -O3 by 3-4%.  OK for trunk?

Thanks.


H.J.
---
2010-12-06  H.J. Lu  <hongjiu.lu@intel.com>

	* config/i386/i386.c (m_COREI7): New.
	(initial_ix86_tune_features): Turn on
	X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL and
	X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL for Core i7.

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index fafa299..36bb154 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -1644,6 +1644,7 @@ const struct processor_costs *ix86_cost = &pentium_cost;
 #define m_CORE2_64  (1<<PROCESSOR_CORE2_64)
 #define m_COREI7_32  (1<<PROCESSOR_COREI7_32)
 #define m_COREI7_64  (1<<PROCESSOR_COREI7_64)
+#define m_COREI7  (m_COREI7_32 | m_COREI7_64)
 #define m_CORE2I7_32  (m_CORE2_32 | m_COREI7_32)
 #define m_CORE2I7_64  (m_CORE2_64 | m_COREI7_64)
 #define m_CORE2I7  (m_CORE2I7_32 | m_CORE2I7_64)
@@ -1810,10 +1811,10 @@ static unsigned int initial_ix86_tune_features[X86_TUNE_LAST] = {
   | m_AMDFAM10 | m_BDVER1,
 
   /* X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL */
-  m_AMDFAM10 | m_BDVER1,
+  m_AMDFAM10 | m_BDVER1 | m_COREI7,
 
   /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL */
-  m_BDVER1,
+  m_BDVER1 | m_COREI7,
 
   /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL */
   m_BDVER1,

Attachment: gcc-4.6-20101202-corei7.xlsx
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