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Re: Vector permutation support for x86
- From: "H.J. Lu" <hjl dot tools at gmail dot com>
- To: Richard Henderson <rth at redhat dot com>
- Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>, Sebastian Pop <sebastian dot pop at amd dot com>
- Date: Mon, 22 Nov 2010 17:53:40 -0800
- Subject: Re: Vector permutation support for x86
- References: <4B0DEE40.firstname.lastname@example.org> <email@example.com> <firstname.lastname@example.org>
On Fri, Apr 16, 2010 at 9:03 PM, H.J. Lu <email@example.com> wrote:
> On Fri, Nov 27, 2009 at 3:45 PM, H.J. Lu <firstname.lastname@example.org> wrote:
>> On Wed, Nov 25, 2009 at 6:56 PM, Richard Henderson <email@example.com> wrote:
>>> The following implements the builtin_vec_perm hook so that the vectorizer
>>> can do its SLP thing. ?As noted elsewhere, ISAs before SSSE3 cannot
>>> arbitrarily permute, so this complicates things a bit. ?But even given
>>> SSSE3, the arbitrary two-vector permute costs 3 insns, and so we would want
>>> to do most of this work to find the 1 and 2 insn special cases.
>>> For the AMD folk: I tried to support the vpperm insn from the XOP ISA, but
>>> there seems to be some disconnect between trunk binutils and trunk gcc wrt
>>> vpperm. ?This can be seen in the failure of the new test "vperm-v4si-2x.c".
>>> ?I'm looking at the XOP spec labeled "Pub No 43479, Rev 3.03, May 2009", and
>>> what gcc is emitting looks ok. ?But I've already been bitten by an
>>> out-of-date AVX spec during this adventure, so I'd appreciate some
>>> Tested on an i7 machine (i.e. sse4.2).
>> This caused:
> This also caused:
This also caused: