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Re: [patch 1/2] AMD bdver2 processors - BMI
On 10/28/2010 02:37 PM, Quentin Neill wrote:
> +(define_insn "bmi_tzcnt_<mode>"
> + [(set (match_operand:SWI248 0 "register_operand" "=r")
> + (unspec:SWI248 [(match_operand:SWI248 1 "nonimmediate_operand" "rm")]
> + UNSPEC_TZCNT))
> + (clobber (reg:CC FLAGS_REG))]
Um, why didn't you modify the CTZ named pattern as we discussed?
> +__blsi_u64 (unsigned long long __X)
> +{
> + unsigned long long tmp = (__X) & (__X * -1);
Use unary negate instead of mult by -1.
> +(define_insn "bmi_bextr_<mode>"
> + [(set (match_operand:SWI48 0 "register_operand" "=r")
> + (unspec:SWI48 [(match_operand:SWI48 1 "nonimmediate_operand" "rm")
> + (match_operand:SWI48 2 "register_operand" "r")]
> + UNSPEC_BEXTR))
> + (clobber (reg:CC FLAGS_REG))]
> + "TARGET_BMI"
> + "bextr\t{%2, %1, %0|%0, %1, %2}"
> + [(set_attr "type" "bitmanip")
> + (set_attr "mode" "<MODE>")])
You can accept the immediate form of BEXTR here as well. While
the immediate form can be described more accurately in generic
rtl and the register form is ... complicated, we don't need to
punish the register form by actually requiring a register.
Err... nevermind. Save that change until the TBM patterns are
ready to go in. I must say it's rather confusing having the
two forms be in two separate ISA extensions.
r~