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Re: Core 2 and Core i7 tuning


> >> +  2,					/* cost of moving SSE register
> >> */
> > 
> > Too high?
> 
> Likely.  I changed that in the pipeline description IIRC but this
> probably needs changing as well.

Those costs are not cycles, they are relative to reg-reg move that has cost
of 2.  So setting it to 1 makes SSE move cheaper than integer move. I see
that geode cost table is wrong here.

Honza
> 
> > 1 now. Inter unit moves got a lot cheaper.
> 
> As far as I know there are still stalls?
> 
> >> +  32,					/* size of l1 cache.  */
> >> +  256,					/* size of l2 cache.  */
> > 
> > I used the L3 here. Makes more sense?
> 
> No idea.
> 
> >> +  3,					/* Branch cost */
> >> +  COSTS_N_INSNS (3),			/* cost of FADD and FSUB insns.  */
> >> +  COSTS_N_INSNS (5),			/* cost of FMUL instruction.  */
> >> +  COSTS_N_INSNS (32),			/* cost of FDIV instruction.  */
> >> +  COSTS_N_INSNS (1),			/* cost of FABS instruction.  */
> >> +  COSTS_N_INSNS (1),			/* cost of FCHS instruction.  */
> >> +  COSTS_N_INSNS (58),			/* cost of FSQRT
> >> instruction.  */
> > 
> > I suspect some of these costs are also outdated, but needs measurements.
> 
> FADD and FMUL are correct, I think, but Maxim pointed me at an earlier
> patch from Vlad which got better results by changing them.
> 
> >>    /* X86_TUNE_PAD_RETURNS */
> >> -  m_AMD_MULTIPLE | m_CORE2 | m_GENERIC,
> >> +  m_AMD_MULTIPLE | m_GENERIC,
> > 
> > Not sure why?
> 
> Everything I looked at seemed to say this is an AMD-only thing.
> 
> 
> Bernd


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