This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [PATCH] Optimize nested SIGN_EXTENDs/ZERO_EXTENDs (PR target/45336)
On Fri, Aug 20, 2010 at 10:27 AM, Jakub Jelinek <jakub@redhat.com> wrote:
> On Fri, Aug 20, 2010 at 09:56:41AM -0700, H.J. Lu wrote:
>> Can we optimize out sign_extend in:
>>
>> (insn:TI 9 7 10 (set (reg:SI 0 ax [orig:68 D.6819 ] [68])
>> ? ? ? ? (zero_extend:SI (vec_select:QI (reg:V16QI 21 xmm0 [orig:64 x ] [64])
>> ? ? ? ? ? ? ? ? (parallel [
>> ? ? ? ? ? ? ? ? ? ? ? ? (const_int 4 [0x4])
>> ? ? ? ? ? ? ? ? ? ? ]))))
>> /export/build/gnu/gcc/build-x86_64-linux/gcc/include/smmintrin.h:442 1681
>> {*sse4_1_pextrb}
>> ? ? ?(expr_list:REG_DEAD (reg:V16QI 21 xmm0 [orig:64 x ] [64])
>> ? ? ? ? (nil)))
>>
>> (insn:TI 10 9 18 (set (reg:DI 0 ax [orig:67 D.6819 ] [67])
>> ? ? ? ? (sign_extend:DI (reg:SI 0 ax [orig:68 D.6819 ] [68]))) foo.c:3 126
>> {extendsidi2_rex64}
>> ? ? ?(nil))
>
> I guess only if there is a
> ?[(set (match_operand:DI 0 "register_operand" "=r")
> ? ? ? ?(zero_extend:DI
> ? ? ? ? ?(vec_select:QI
> ? ? ? ? ? ?(match_operand:V16QI 1 "register_operand" "x")
> ? ? ? ? ? ?(parallel [(match_operand:SI 2 "const_0_to_15_operand" "n")]))))]
> pattern for TARGET_64BIT.
> Not sure what exactly is
> pextrb ..., %ecx
> insn doing to the upper 32 bits of %rcx, if it clears them, such an insn
> would be nice to have in sse.md (similarly for pextrw/pextrd).
> If there is such a pattern, I think with my simplify_* changes the combiner
> will do its job.
>
We can certain add them. I will give it a try.
--
H.J.