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Re: Vector misalignment
On Mon, Aug 16, 2010 at 11:18:04AM -0700, Andrew Pinski wrote:
> On Mon, Aug 16, 2010 at 11:15 AM, Artem Shinkarov
> <email@example.com> wrote:
> > would produce no warnings, but causes a segmentation fault on intel
> > and powerpc architecture.
> How will it produce a seg fault on PPC (VMX) targets? The VMX load
> instructions don't fault but rather just use the "aligned" address.
True for VMX (altivec) target, but the VSX instruction set in power7 no longer
ignores the bottom bits for the vector loads/stores, and so could potentially
have an alignment failure.
However, the VSX instructions will not generate an alignment trap if the pointer
is approprilately aligned for 2 or 4 bytes (depending on the memory reference
Michael Meissner, IBM
5 Technology Place Drive, M/S 2757, Westford, MA 01886-3141, USA