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Re: Vector comparison
On Sun, Aug 15, 2010 at 10:03 PM, Joseph S. Myers
<joseph@codesourcery.com> wrote:
> On Sun, 15 Aug 2010, Artem Shinkarov wrote:
>
>> On Sun, Aug 15, 2010 at 7:45 PM, Joseph S. Myers
>> <joseph@codesourcery.com> wrote:
>> > On Sun, 15 Aug 2010, Artem Shinkarov wrote:
>> >
>> >> This patch implements vector comparison according to OpenCL standard.
>> >
>> > Suppose your target's vector comparison instructions encode the result
>> > some way other than a vector of 0 and -1 values. ?How effectively can such
>> > instructions be used in the context of your patch?
>>
>> SSE and AltiVec at least define vector comparison result as a vector
>> of 0 and -1. So I think that this would be an exotic architecture (but
>> I'm not sure). Anyway, if the target returns boolean value, then the
>
> I'm thinking in particular of TI C64X (which can probably be considered an
> exotic architecture in lots of ways), where vector comparisons set the
> low-order two or four bits of the target register and then you need a
> separate XPND2 or XPND4 instruction to convert this to a vector with 0 and
> -1 values. ?The comparison instructions are single-cycle while XPND2 and
> XPND4 are two-cycle instructions; it would be nice to avoid excess
> instructions where possible. ?(The GCC port for C6X exists based on 4.4
> but isn't yet ready for upstream submission; I sent the binutils port
> upstream in March.)
The current patch would support this by always emitting builtins for
the separate XPND2/4 instructions. Dependent on the use (I expect
that openCL code will mostly use the comparison result as a mask,
not reduce it to a single bool) the not needed result could be optimized
by combine.
Richard.
> --
> Joseph S. Myers
> joseph@codesourcery.com