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[PATCH,rs6000] disable mfcr pattern for TARGET_ISEL

mfcr can be a slow instruction, particular for multiple-issue
processors, where it requires serializing the instruction stream to
ensure that CR has been properly updated.  The primary pattern where
mfcr occurs deals with moving an individual bit from CR to a GPR.  This
pattern not only uses mfcr, but also binds the mfcr and accompanying
rlwinm together instead of permitting them to be scheduled separately.

On TARGET_ISEL processors, however, we can improve the matter somewhat
by using isel instead of mfcr.  With isel, there's no need to
synchronize on CR as a whole, just an individual field.  The
instructions that load zero and one can also be scheduled separately
from the isel itself.  The patch below enables this improvement by
turning off the aforementioned mfcr/rlwinm pattern for TARGET_ISEL

The patch could be improved; there's a TARGET_POWERPC64 pattern that's
identical save for the modes of registers slightly further on in the
file.  I don't have a power7 system to test the equivalent 64-bit path
on, but if somebody was willing to test on such a system for me, I could
tweak the patch accordingly.  (Such a tweaked patch could also use mode
iterators, which would be an improvement.)

Tested with cross to powerpc-eabispe.  OK to commit?


	* config/rs6000/ (define_insn ""): Enable only for
	!TARGET_ISEL targets.

Index: config/rs6000/
--- config/rs6000/	(revision 162348)
+++ config/rs6000/	(working copy)
@@ -13052,7 +13052,7 @@ (define_insn ""
 	(match_operator:SI 1 "scc_comparison_operator"
 			   [(match_operand 2 "cc_reg_operand" "y")
 			    (const_int 0)]))]
-  ""
   "mfcr %0%Q2\;{rlinm|rlwinm} %0,%0,%J1,1"
   [(set (attr "type")
      (cond [(ne (symbol_ref "TARGET_MFCRF") (const_int 0))

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