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Re: [vect] Ask for review and approving the patch about vect and loongson


2010/7/9 Richard Guenther <richard.guenther@gmail.com>:
>
> How about splitting the patch?
>
> Richard.
>

Thanks. I put the patch separately now. And the ChageLogs,

gcc/ChangeLog
  * sourcebuild.texi: Remove duplicated item vect_int_mult.
  * loongson.md: Add define_expand for standard names mulm3 (VH),
ashrm3 (VWH), lshrm3 (VWH) to generate SIMD automatically.

testsuite/ChangeLog
  * fast-math-vect-reduc-8.c: Move dg-require-effective-target after dg-do.
  * vect.exp: Go on running the testsuite when the target is mips*
  * target-supports.exp: Check loongson target in vector specific attributes.


Thanks,
Eric
Index: doc/sourcebuild.texi
===================================================================
--- doc/sourcebuild.texi	(revision 161865)
+++ doc/sourcebuild.texi	(working copy)
@@ -1324,11 +1324,6 @@ Target supports hardware vectors of @cod
 @item vect_int
 Target supports hardware vectors of @code{int}.
 
-@item vect_int_mult
-Target supports a vector widening multiplication of @code{short} operands
-into an @code{int} result, or supports promotion (unpacking) from
-@code{short} to @code{int} and a non-widening multiplication of @code{int}.
-
 @item vect_long
 Target supports hardware vectors of @code{long}.
 
Index: testsuite/gcc.dg/vect/fast-math-vect-reduc-8.c
===================================================================
--- testsuite/gcc.dg/vect/fast-math-vect-reduc-8.c	(revision 161865)
+++ testsuite/gcc.dg/vect/fast-math-vect-reduc-8.c	(working copy)
@@ -1,5 +1,5 @@
-/* { dg-require-effective-target vect_float } */
 /* { dg-do compile } */
+/* { dg-require-effective-target vect_float } */
 
 #include "tree-vect.h"
 
Index: testsuite/gcc.dg/vect/vect.exp
===================================================================
--- testsuite/gcc.dg/vect/vect.exp	(revision 161865)
+++ testsuite/gcc.dg/vect/vect.exp	(working copy)
@@ -76,10 +76,10 @@ if  [istarget "powerpc-*paired*"]  {
     } else {
 	set dg-do-what-default compile
     }
-} elseif { [istarget "mips*-*-*"]
-	   && [check_effective_target_mpaired_single]
-	   && [check_effective_target_nomips16] } {
-    lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+} elseif { [istarget "mips*-*-*"] && [check_effective_target_nomips16] } {
+    if { [check_effective_target_mpaired_single] } {
+        lappend DEFAULT_VECTCFLAGS "-mpaired-single"
+    }
     set dg-do-what-default run
 } elseif [istarget "sparc*-*-*"] {
     lappend DEFAULT_VECTCFLAGS "-mcpu=ultrasparc" "-mvis"
Index: testsuite/lib/target-supports.exp
===================================================================
--- testsuite/lib/target-supports.exp	(revision 161865)
+++ testsuite/lib/target-supports.exp	(working copy)
@@ -1493,7 +1493,8 @@ proc check_effective_target_vect_int { }
 	      || [istarget sparc*-*-*]
 	      || [istarget alpha*-*-*]
 	      || [istarget ia64-*-*] 
-	      || [check_effective_target_arm32] } {
+	      || [check_effective_target_arm32]
+              || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	   set et_vect_int_saved 1
 	}
     }
@@ -2029,7 +2030,8 @@ proc check_effective_target_vect_shift {
 	     || [istarget ia64-*-*]
 	     || [istarget i?86-*-*]
 	     || [istarget x86_64-*-*]
-	     || [check_effective_target_arm32] } {
+	     || [check_effective_target_arm32]
+             || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	   set et_vect_shift_saved 1
 	}
     }
@@ -2143,7 +2145,8 @@ proc check_effective_target_vect_no_int_
 	set et_vect_no_int_max_saved 0
 	if { [istarget sparc*-*-*]
 	     || [istarget spu-*-*]
-	     || [istarget alpha*-*-*] } {
+	     || [istarget alpha*-*-*]
+             || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	    set et_vect_no_int_max_saved 1
 	}
     }
@@ -2516,7 +2519,8 @@ proc check_effective_target_vect_no_alig
 	if { [istarget mipsisa64*-*-*]
 	     || [istarget sparc*-*-*]
 	     || [istarget ia64-*-*]
-	     || [check_effective_target_arm32] } { 
+	     || [check_effective_target_arm32]
+             || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	    set et_vect_no_align_saved 1
 	}
     }
@@ -2707,7 +2711,8 @@ proc check_effective_target_vect_short_m
 	     || [istarget i?86-*-*]
 	     || [istarget x86_64-*-*]
              || [istarget powerpc*-*-*]
-             || [check_effective_target_arm32] } {
+             || [check_effective_target_arm32]
+             || ([istarget mips*-*-*] && [check_effective_target_mips_loongson]) } {
 	   set et_vect_short_mult_saved 1
 	}
     }
Index: config/mips/loongson.md
===================================================================
--- config/mips/loongson.md	(revision 161865)
+++ config/mips/loongson.md	(working copy)
@@ -352,6 +352,16 @@
   "pmulh<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fmul")])
 
+;; Standard pattern mulm3
+(define_expand "mul<mode>3"
+  [(set (match_operand:VH 0 "register_operand" "=f")
+        (unspec:VH [(match_operand:VH 1 "register_operand" "f")
+                    (match_operand:VH 2 "register_operand" "f")]
+                   UNSPEC_LOONGSON_PMULL))]
+  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
+  "")
+
+
 ;; Multiply signed integers and store low result.
 (define_insn "loongson_pmull<V_suffix>"
   [(set (match_operand:VH 0 "register_operand" "=f")
@@ -421,6 +431,14 @@
   "psll<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fmul")])
 
+;; Standard pattern ashrm3
+(define_expand "ashr<mode>3"
+  [(set (match_operand:VWH 0 "register_operand" "=f")
+        (ashiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
+                      (match_operand:SI 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
+  "")
+
 ;; Shift right arithmetic.
 (define_insn "loongson_psra<V_suffix>"
   [(set (match_operand:VWH 0 "register_operand" "=f")
@@ -430,6 +448,14 @@
   "psra<V_suffix>\t%0,%1,%2"
   [(set_attr "type" "fdiv")])
 
+;; Standard pattern lshrm3
+(define_expand "lshr<mode>3"
+  [(set (match_operand:VWH 0 "register_operand" "=f")
+        (lshiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
+                      (match_operand:SI 2 "register_operand" "f")))]
+  "TARGET_HARD_FLOAT && TARGET_LOONGSON_VECTORS"
+  "")
+
 ;; Shift right logical.
 (define_insn "loongson_psrl<V_suffix>"
   [(set (match_operand:VWH 0 "register_operand" "=f")

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