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Re: [PING] [PATCH: PR target/42879] Replace "tst r3, 1" with "lsls r3, r3, 31" in thumb2


On Sat, 2010-05-01 at 13:15 +0800, Carrot Wei wrote:
> On Fri, Apr 30, 2010 at 4:27 PM, Richard Earnshaw <rearnsha@arm.com> wrote:
> >> Since only when both registers are LO_REGS, then the lsls will be
> >> encoded as 16bit. Otherwise it is 32 bit, no better than current tst
> >> instruction.
> >>
> >
> > Except that at the time the pattern is generated we don't know whether
> > or not HI or LO regs will be used (since this is in combine and we are
> > still using pseudos).
> >
> >> With this patch should it fall back to tst instruction when there are HI_REGS?
> >
> > So your pattern needs to handle the fall-back case as well, when we want
> > to generate TST rather than LSLS (note you can use 'X' as a constraint
> > for the output in this case to say that you don't need a register).
> >
> 
> According to your suggestion, I added a new insn pattern to handle it on thumb2.
> 
> It passed the regression tests on arm qemu.
> 
> 
> ChangeLog:
> 2010-05-01  Wei Guozhi  <carrot@google.com>
> 
>        PR target/42879
>        * config/arm/thumb2.md (thumb2_tlobits_cbranch): New insn pattern.
> 
> ChangeLog:
> 2010-05-01  Wei Guozhi  <carrot@google.com>
> 
>        PR target/42879
>        * gcc.target/arm/pr42879.c: New testcase.

Thumb2 always uses unified syntax, so there's no need for the legacy lsl
form.

Otherwise, OK

R.


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