This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [patch] Hookize SMALL_REGISTER_CLASSES
- From: Jakub Jelinek <jakub at redhat dot com>
- To: Steven Bosscher <stevenb dot gcc at gmail dot com>
- Cc: Uros Bizjak <ubizjak at gmail dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>, Richard Guenther <richard dot guenther at gmail dot com>
- Date: Mon, 3 May 2010 21:54:07 +0200
- Subject: Re: [patch] Hookize SMALL_REGISTER_CLASSES
- References: <4BDF240D.7060703@gmail.com> <l2n571f6b511005031239j4c2142cfjac4ea2337051908a@mail.gmail.com>
- Reply-to: Jakub Jelinek <jakub at redhat dot com>
On Mon, May 03, 2010 at 09:39:01PM +0200, Steven Bosscher wrote:
> >> + ?/* Any mode that is OK for SSE or AVX registers is not likely
> >> + ? ? to be allocated to a small class. ?*/
> >> + ?if (TARGET_SSE_MATH
> >> + ? ? ?&& (SSE_FLOAT_MODE_P (mode) || VECTOR_MODE_P (mode)))
> >> + ? ?return false;
> >> +
> >> + ?/* AMD64 has 16 registers for >=32 bits integers. ?This is not
> >> + ? ? large compared to RISC/VLIW architectures, but it is big
> >> + ? ? enough for us to consider it non-small. ?*/
> >> + ?if (SCALAR_INT_MODE_P (mode) && GET_MODE_SIZE (mode) >= 32)
> >> + ? ?return false;
> >
> > As mentioned elsewhere, all registers can be accessed as 8bit or 16bit
> > in addition to 32bit and 64bit on x86_64.
>
> Yes, I know. So what does that mean? Should I change this to always
> return false for SCALAR_INT_MODE_P modes?
Aren't
AREG, DREG, CREG, BREG, SIREG, DIREG,
AD_REGS, /* %eax/%edx for DImode */
SSE_FIRST_REG,
classes small though? Aren't we going to ICE frequently whenever x86-64
code uses these classes say in inline asm?
Jakub