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Re: [PATCH: PR target/42879] Replace "tst r3, 1" with "lsls r3, r3, 31" in thumb2
Ping
On Mon, Apr 26, 2010 at 2:33 PM, Carrot Wei <carrot@google.com> wrote:
> Hi
>
> Both "tst r3, 1" and "lsls r3, r3, 31" have the same effect when used to set
> conditions for following branch. But lsls is a 16 bit instruction and tst is a
> 32 bit instruction. So we prefer lsls in thumb2.
>
> Thumb1 already has an insn pattern "*tlobits_cbranch" to do this, this patch
> enables it for thumb2.
>
> Test:
> Regression tests on arm qemu.
>
>
> ChangeLog:
> 2010-04-26 ?Wei Guozhi ?<carrot@google.com>
>
> ? ? ? ?PR target/42879
> ? ? ? ?* config/arm/arm.md (tlobits_cbranch): Enable it for Thumb2.
>
> ChangeLog:
> 2010-04-26 ?Wei Guozhi ?<carrot@google.com>
>
> ? ? ? ?PR target/42879
> ? ? ? ?* gcc.target/arm/pr42879.c: New testcase.
>
> thanks
> Guozhi
>
>
> Index: arm.md
> ===================================================================
> --- arm.md ? ? ?(revision 158717)
> +++ arm.md ? ? ?(working copy)
> @@ -6992,7 +6992,7 @@
> ? ? ? ? (label_ref (match_operand 3 "" ""))
> ? ? ? ? (pc)))
> ? ?(clobber (match_scratch:SI 4 "=l"))]
> - ?"TARGET_THUMB1"
> + ?"TARGET_THUMB"
> ? "*
> ? {
> ? rtx op[3];
> @@ -7000,7 +7000,10 @@
> ? op[1] = operands[1];
> ? op[2] = GEN_INT (32 - INTVAL (operands[2]));
>
> - ?output_asm_insn (\"lsl\\t%0, %1, %2\", op);
> + ?if (TARGET_THUMB1)
> + ? ?output_asm_insn (\"lsl\\t%0, %1, %2\", op);
> + ?else
> + ? ?output_asm_insn (\"lsls\\t%0, %1, %2\", op);
> ? switch (get_attr_length (insn))
> ? ? {
> ? ? case 4: ?return \"b%d0\\t%l3\";
>
>
> Index: pr42879.c
> ===================================================================
> --- pr42879.c ? (revision 0)
> +++ pr42879.c ? (revision 0)
> @@ -0,0 +1,15 @@
> +/* { dg-options "-march=armv7-a -mthumb -Os" } ?*/
> +/* { dg-final { scan-assembler "lsls" } } */
> +
> +struct A
> +{
> + ?int v:1;
> +};
> +
> +int bar();
> +int foo(struct A* p)
> +{
> + ?if (p->v)
> + ? ?return 1;
> + ?return bar();
> +}
>