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Re: [PATCH, ARM] Low interrupt latency support (avoiding ldm/stm)
- From: Julian Brown <julian at codesourcery dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: paul at codesourcery dot com, rearnsha at arm dot com, rearnsha at arm dot com, paul at codesourcery dot com
- Date: Mon, 26 Apr 2010 14:16:32 +0100
- Subject: Re: [PATCH, ARM] Low interrupt latency support (avoiding ldm/stm)
- References: <20091127175025.7fb6ceae@rex.config> <571f6b510911270954u303725a4l8e85436ee6b1ba08@mail.gmail.com> <20091127183049.79a0d201@rex.config>
On Fri, 27 Nov 2009 18:30:49 +0000
Julian Brown <julian@codesourcery.com> wrote:
> This patch (originally by Vladimir Prus) provides support for
> improving interrupt latency by avoiding LDM/STM instructions, which
> may not be interruptible mid-operation on some (all?) cores. This is
> achieved by adding a compilation option (-mlow-interrupt-latency),
> since code without multi-reg loads/stores will generally be both
> larger and slower.
(ISTR Paul mentioned when I posted this patch before that high-latency
interrupts when using LDM/STM were only a problem for certain ARM ISA
licensees, but don't affect ARM's own cores, FWIW.)
> > Isn't GCC 4.5 in stage3? Where no new functionality should be added?
> > Makes the timing of this patch not very appropriate, I would say.
>
> Huh, so it is. Consider this patch retracted for the time being then:
> it's undeniably a new feature.
We're in stage 1 now: can this patch be considered again?
Thanks,
Julian