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Re: [Patch ARM] Fixup testsuite for gcc.target/neon-modes-1.c
On Sat, Apr 10, 2010 at 02:23:27PM +0100, Ramana Radhakrishnan wrote:
> Ok that sounds neat. I have no objections to withdrawing my patch if
> there's something better that Dan's got and the original intent of
> add_options_for_arm_neon was beyond my simple interpretation.
I didn't update sourcebuild.texi previously, so thank you and Rainer
for pointing that out. Here's my full patch.
The reason for the complexity is testing -mfloat-abi=hard. You don't
want to add -mfloat-abi=softfp to a runtime test in this case, but
ideally you don't want to suppress the test either. They're
incompatible and both acceptable.
Disclaimer: I have not retested this lately, only the info parts.
Want me to?
--
Daniel Jacobowitz
CodeSourcery
2010-04-15 Daniel Jacobowitz <dan@codesourcery.com>
gcc/
* config/arm/neon-testgen.ml: Use dg-add-options arm_neon.
* doc/sourcebuild.texi (Effective-Target Keywords): Update arm_neon_ok
description. Add arm_neon_fp16_ok.
(Add Options): Add arm_neon and arm_neon_fp16.
gcc/testsuite/
* gcc/target/arm/neon/: Regenerated test cases.
* gcc.target/arm/neon/polytypes.c,
gcc.target/arm/neon-vmla-1.c, gcc.target/arm/neon-vmls-1.c,
gcc.target/arm/neon-cond-1.c, gcc.dg/torture/arm-fp16-ops-8.c,
gcc.dg/torture/arm-fp16-ops-7.c, g++.dg/ext/arm-fp16/arm-fp16-ops-7.C,
g++.dg/ext/arm-fp16/arm-fp16-ops-8.C, g++.dg/abi/mangle-neon.C: Use
dg-add-options arm_neon.
* gcc.target/arm/fp16-compile-vcvt.c, gcc.dg/torture/arm-fp16-ops-5.c,
gcc.dg/torture/arm-fp16-ops-6.c, g++.dg/ext/arm-fp16/arm-fp16-ops-5.C,
g++.dg/ext/arm-fp16/arm-fp16-ops-6.C: Use dg-add-options arm_neon_fp16
and arm_neon_fp16_ok.
* gcc.dg/vect/vect.exp, g++.dg/vect/vect.exp,
gfortran.dg/vect/vect.exp: Use add_options_for_arm_neon.
* lib/target-supports.exp (add_options_for_arm_neon): New.
(check_effective_target_arm_neon_ok_nocache): New, from
check_effective_target_arm_neon_ok. Check multiple possibilities.
(check_effective_target_arm_neon_ok): Use
check_effective_target_arm_neon_ok_nocache.
(add_options_for_arm_neon_fp16)
(check_effective_target_arm_neon_fp16_ok)
check_effective_target_arm_neon_fp16_ok_nocache): New.
(check_effective_target_arm_neon_hw): Use add_options_for_arm_neon.
Index: gcc/testsuite/gcc.target/arm/neon/polytypes.c
===================================================================
--- gcc/testsuite/gcc.target/arm/neon/polytypes.c (revision 254492)
+++ gcc/testsuite/gcc.target/arm/neon/polytypes.c (revision 254493)
@@ -3,7 +3,7 @@
/* { dg-do compile } */
/* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-mfpu=neon -mfloat-abi=softfp" } */
+/* { dg-add-options arm_neon } */
#include <arm_neon.h>
Index: gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c
===================================================================
--- gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c (revision 254492)
+++ gcc/testsuite/gcc.target/arm/fp16-compile-vcvt.c (revision 254493)
@@ -1,6 +1,7 @@
/* { dg-do compile } */
-/* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-options "-mfp16-format=ieee" } */
+/* { dg-add-options arm_neon_fp16 } */
/* Test generation of VFP __fp16 instructions. */
Index: gcc/testsuite/gcc.target/arm/neon-vmla-1.c
===================================================================
--- gcc/testsuite/gcc.target/arm/neon-vmla-1.c (revision 254492)
+++ gcc/testsuite/gcc.target/arm/neon-vmla-1.c (revision 254493)
@@ -1,5 +1,6 @@
/* { dg-require-effective-target arm_neon_hw } */
-/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-add-options arm_neon } */
/* { dg-final { scan-assembler "vmla\\.f32" } } */
/* Verify that VMLA is used. */
Index: gcc/testsuite/gcc.target/arm/neon-vmls-1.c
===================================================================
--- gcc/testsuite/gcc.target/arm/neon-vmls-1.c (revision 254492)
+++ gcc/testsuite/gcc.target/arm/neon-vmls-1.c (revision 254493)
@@ -1,5 +1,6 @@
/* { dg-require-effective-target arm_neon_hw } */
-/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp -ftree-vectorize" } */
+/* { dg-options "-O2 -ftree-vectorize" } */
+/* { dg-add-options arm_neon } */
/* { dg-final { scan-assembler "vmls\\.f32" } } */
/* Verify that VMLS is used. */
Index: gcc/testsuite/gcc.target/arm/neon-cond-1.c
===================================================================
--- gcc/testsuite/gcc.target/arm/neon-cond-1.c (revision 254492)
+++ gcc/testsuite/gcc.target/arm/neon-cond-1.c (revision 254493)
@@ -1,6 +1,7 @@
/* { dg-do run } */
/* { dg-require-effective-target arm_neon_hw } */
-/* { dg-options "-O2 -mfpu=neon -mfloat-abi=softfp" } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_neon } */
/* Check that the arm_final_prescan_insn ccfsm code does not try to
* conditionally execute NEON instructions. */
#include <arm_neon.h>
Index: gcc/testsuite/gcc.dg/torture/arm-fp16-ops-8.c
===================================================================
--- gcc/testsuite/gcc.dg/torture/arm-fp16-ops-8.c (revision 254492)
+++ gcc/testsuite/gcc.dg/torture/arm-fp16-ops-8.c (revision 254493)
@@ -1,7 +1,8 @@
/* Test various operators on __fp16 and mixed __fp16/float operands. */
/* { dg-do compile { target arm*-*-* } } */
/* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon -mfloat-abi=softfp" } */
+/* { dg-options "-mfp16-format=ieee -ffast-math" } */
+/* { dg-add-options arm_neon } */
#include "arm-fp16-ops.h"
Index: gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c
===================================================================
--- gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c (revision 254492)
+++ gcc/testsuite/gcc.dg/torture/arm-fp16-ops-5.c (revision 254493)
@@ -1,7 +1,8 @@
/* Test various operators on __fp16 and mixed __fp16/float operands. */
/* { dg-do compile { target arm*-*-* } } */
-/* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-options "-mfp16-format=ieee" } */
+/* { dg-add-options arm_neon_fp16 } */
#include "arm-fp16-ops.h"
Index: gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c
===================================================================
--- gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c (revision 254492)
+++ gcc/testsuite/gcc.dg/torture/arm-fp16-ops-6.c (revision 254493)
@@ -1,7 +1,8 @@
/* Test various operators on __fp16 and mixed __fp16/float operands. */
/* { dg-do compile { target arm*-*-* } } */
-/* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon-fp16 -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-options "-mfp16-format=ieee -ffast-math" } */
+/* { dg-add-options arm_neon_fp16 } */
#include "arm-fp16-ops.h"
Index: gcc/testsuite/gcc.dg/torture/arm-fp16-ops-7.c
===================================================================
--- gcc/testsuite/gcc.dg/torture/arm-fp16-ops-7.c (revision 254492)
+++ gcc/testsuite/gcc.dg/torture/arm-fp16-ops-7.c (revision 254493)
@@ -1,7 +1,8 @@
/* Test various operators on __fp16 and mixed __fp16/float operands. */
/* { dg-do compile { target arm*-*-* } } */
/* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-mfp16-format=ieee -mfpu=neon -mfloat-abi=softfp" } */
+/* { dg-options "-mfp16-format=ieee" } */
+/* { dg-add-options arm_neon } */
#include "arm-fp16-ops.h"
Index: gcc/testsuite/gcc.dg/vect/vect.exp
===================================================================
--- gcc/testsuite/gcc.dg/vect/vect.exp (revision 254492)
+++ gcc/testsuite/gcc.dg/vect/vect.exp (revision 254493)
@@ -97,7 +97,7 @@ if [istarget "powerpc-*paired*"] {
} elseif [istarget "ia64-*-*"] {
set dg-do-what-default run
} elseif [is-effective-target arm_neon_ok] {
- lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp"
+ eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
Index: gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C
===================================================================
--- gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C (revision 254492)
+++ gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-5.C (revision 254493)
@@ -1,7 +1,8 @@
/* Test various operators on __fp16 and mixed __fp16/float operands. */
/* { dg-do compile { target arm*-*-* } } */
-/* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-mfp16-format=ieee -mfpu=neon-fp16 -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-options "-mfp16-format=ieee" } */
+/* { dg-add-options arm_neon_fp16 } */
#include "arm-fp16-ops.h"
Index: gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C
===================================================================
--- gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C (revision 254492)
+++ gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-6.C (revision 254493)
@@ -1,7 +1,8 @@
/* Test various operators on __fp16 and mixed __fp16/float operands. */
/* { dg-do compile { target arm*-*-* } } */
-/* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon-fp16 -mfloat-abi=softfp" } */
+/* { dg-require-effective-target arm_neon_fp16_ok } */
+/* { dg-options "-mfp16-format=ieee -ffast-math" } */
+/* { dg-add-options arm_neon_fp16 } */
#include "arm-fp16-ops.h"
Index: gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-7.C
===================================================================
--- gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-7.C (revision 254492)
+++ gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-7.C (revision 254493)
@@ -1,7 +1,8 @@
/* Test various operators on __fp16 and mixed __fp16/float operands. */
/* { dg-do compile { target arm*-*-* } } */
/* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-mfp16-format=ieee -mfpu=neon -mfloat-abi=softfp" } */
+/* { dg-options "-mfp16-format=ieee" } */
+/* { dg-add-options arm_neon } */
#include "arm-fp16-ops.h"
Index: gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-8.C
===================================================================
--- gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-8.C (revision 254492)
+++ gcc/testsuite/g++.dg/ext/arm-fp16/arm-fp16-ops-8.C (revision 254493)
@@ -1,7 +1,8 @@
/* Test various operators on __fp16 and mixed __fp16/float operands. */
/* { dg-do compile { target arm*-*-* } } */
/* { dg-require-effective-target arm_neon_ok } */
-/* { dg-options "-mfp16-format=ieee -ffast-math -mfpu=neon -mfloat-abi=softfp" } */
+/* { dg-options "-mfp16-format=ieee -ffast-math" } */
+/* { dg-add-options arm_neon } */
#include "arm-fp16-ops.h"
Index: gcc/testsuite/g++.dg/vect/vect.exp
===================================================================
--- gcc/testsuite/g++.dg/vect/vect.exp (revision 254492)
+++ gcc/testsuite/g++.dg/vect/vect.exp (revision 254493)
@@ -105,7 +105,7 @@ if [istarget "powerpc-*paired*"] {
} elseif [istarget "ia64-*-*"] {
set dg-do-what-default run
} elseif [is-effective-target arm_neon_ok] {
- lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp"
+ eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
Index: gcc/testsuite/g++.dg/abi/mangle-neon.C
===================================================================
--- gcc/testsuite/g++.dg/abi/mangle-neon.C (revision 254492)
+++ gcc/testsuite/g++.dg/abi/mangle-neon.C (revision 254493)
@@ -2,7 +2,7 @@
// { dg-do compile }
// { dg-require-effective-target arm_neon_ok }
-// { dg-options "-mfpu=neon -mfloat-abi=softfp" }
+// { dg-add-options arm_neon }
#include <arm_neon.h>
Index: gcc/testsuite/lib/target-supports.exp
===================================================================
--- gcc/testsuite/lib/target-supports.exp (revision 254492)
+++ gcc/testsuite/lib/target-supports.exp (revision 254493)
@@ -1408,19 +1408,87 @@ proc check_effective_target_arm_hard_vfp
}
}
+# Add the options needed for NEON. We need either -mfloat-abi=softfp
+# or -mfloat-abi=hard, but if one is already specified by the
+# multilib, use it. Similarly, if a -mfpu option already enables
+# NEON, do not add -mfpu=neon.
+
+proc add_options_for_arm_neon { flags } {
+ if { ! [check_effective_target_arm_neon_ok] } {
+ return "$flags"
+ }
+ global et_arm_neon_flags
+ return "$flags $et_arm_neon_flags"
+}
+
# Return 1 if this is an ARM target supporting -mfpu=neon
-# -mfloat-abi=softfp. Some multilibs may be incompatible with these
-# options.
+# -mfloat-abi=softfp or equivalent options. Some multilibs may be
+# incompatible with these options. Also set et_arm_neon_flags to the
+# best options to add.
+
+proc check_effective_target_arm_neon_ok_nocache { } {
+ global et_arm_neon_flags
+ set et_arm_neon_flags ""
+ if { [check_effective_target_arm32] } {
+ foreach flags {"" "-mfloat-abi=softfp" "-mfpu=neon" "-mfpu=neon -mfloat-abi=softfp"} {
+ if { [check_no_compiler_messages_nocache arm_neon_ok object {
+ #include "arm_neon.h"
+ int dummy;
+ } "$flags"] } {
+ set et_arm_neon_flags $flags
+ return 1
+ }
+ }
+ }
+
+ return 0
+}
proc check_effective_target_arm_neon_ok { } {
+ return [check_cached_effective_target arm_neon_ok \
+ check_effective_target_arm_neon_ok_nocache]
+}
+
+# Add the options needed for NEON. We need either -mfloat-abi=softfp
+# or -mfloat-abi=hard, but if one is already specified by the
+# multilib, use it.
+
+proc add_options_for_arm_neon_fp16 { flags } {
+ if { ! [check_effective_target_arm_neon_fp16_ok] } {
+ return "$flags"
+ }
+ global et_arm_neon_fp16_flags
+ return "$flags $et_arm_neon_fp16_flags"
+}
+
+# Return 1 if this is an ARM target supporting -mfpu=neon-fp16
+# -mfloat-abi=softfp or equivalent options. Some multilibs may be
+# incompatible with these options. Also set et_arm_neon_flags to the
+# best options to add.
+
+proc check_effective_target_arm_neon_fp16_ok_nocache { } {
+ global et_arm_neon_fp16_flags
+ set et_arm_neon_fp16_flags ""
if { [check_effective_target_arm32] } {
- return [check_no_compiler_messages arm_neon_ok object {
- #include "arm_neon.h"
- int dummy;
- } "-mfpu=neon -mfloat-abi=softfp"]
- } else {
- return 0
+ # Always add -mfpu=neon-fp16, since there is no preprocessor
+ # macro for FP16 support.
+ foreach flags {"-mfpu=neon-fp16" "-mfpu=neon-fp16 -mfloat-abi=softfp"} {
+ if { [check_no_compiler_messages_nocache arm_neon_fp16_ok object {
+ #include "arm_neon.h"
+ int dummy;
+ } "$flags"] } {
+ set et_arm_neon_fp16_flags $flags
+ return 1
+ }
+ }
}
+
+ return 0
+}
+
+proc check_effective_target_arm_neon_fp16_ok { } {
+ return [check_cached_effective_target arm_neon_fp16_ok \
+ check_effective_target_arm_neon_fp16_ok_nocache]
}
# Return 1 is this is an ARM target where -mthumb causes Thumb-1 to be
@@ -1459,7 +1527,7 @@ proc check_effective_target_arm_neon_hw
: "0" (a), "w" (b));
return (a != 1);
}
- } "-mfpu=neon -mfloat-abi=softfp"]
+ } [add_options_for_arm_neon ""]]
}
# Return 1 if this is a ARM target with NEON enabled.
Index: gcc/testsuite/gfortran.dg/vect/vect.exp
===================================================================
--- gcc/testsuite/gfortran.dg/vect/vect.exp (revision 254492)
+++ gcc/testsuite/gfortran.dg/vect/vect.exp (revision 254493)
@@ -98,7 +98,7 @@ if [istarget "powerpc-*paired*"] {
} elseif [istarget "ia64-*-*"] {
set dg-do-what-default run
} elseif [is-effective-target arm_neon_ok] {
- lappend DEFAULT_VECTCFLAGS "-mfpu=neon" "-mfloat-abi=softfp"
+ eval lappend DEFAULT_VECTCFLAGS [add_options_for_arm_neon ""]
if [is-effective-target arm_neon_hw] {
set dg-do-what-default run
} else {
Index: gcc/config/arm/neon-testgen.ml
===================================================================
--- gcc/config/arm/neon-testgen.ml (revision 254492)
+++ gcc/config/arm/neon-testgen.ml (revision 254493)
@@ -51,8 +51,8 @@ let emit_prologue chan test_name =
Printf.fprintf chan "/* This file was autogenerated by neon-testgen. */\n\n";
Printf.fprintf chan "/* { dg-do assemble } */\n";
Printf.fprintf chan "/* { dg-require-effective-target arm_neon_ok } */\n";
- Printf.fprintf chan
- "/* { dg-options \"-save-temps -O0 -mfpu=neon -mfloat-abi=softfp\" } */\n";
+ Printf.fprintf chan "/* { dg-options \"-save-temps -O0\" } */\n";
+ Printf.fprintf chan "/* { dg-add-options arm_neon } */\n";
Printf.fprintf chan "\n#include \"arm_neon.h\"\n\n";
Printf.fprintf chan "void test_%s (void)\n{\n" test_name
Index: gcc/doc/sourcebuild.texi
===================================================================
--- gcc/doc/sourcebuild.texi (revision 158388)
+++ gcc/doc/sourcebuild.texi (working copy)
@@ -1497,8 +1497,14 @@ ARM target supports generating NEON inst
Test system supports executing NEON instructions.
@item arm_neon_ok
-ARM Target supports @code{-mfpu=neon -mfloat-abi=softfp}.
-Some multilibs may be incompatible with these options.
+@anchor{arm_neon_ok}
+ARM Target supports @code{-mfpu=neon -mfloat-abi=softfp} or compatible
+options. Some multilibs may be incompatible with these options.
+
+@item arm_neon_fp16_ok
+@anchor{arm_neon_fp16_ok}
+ARM Target supports @code{-mfpu=neon-fp16 -mfloat-abi=softfp} or compatible
+options. Some multilibs may be incompatible with these options.
@item arm_thumb1_ok
ARM target generates Thumb-1 code for @code{-mthumb}.
@@ -1863,6 +1869,16 @@ compliance mode.
@item mips16_attribute
@code{mips16} function attributes.
Only MIPS targets support this feature, and only then in certain modes.
+
+@item arm_neon
+NEON support. Only ARM targets support this feature, and only then
+in certain modes; see the @ref{arm_neon_ok,,arm_neon_ok effective target
+keyword}.
+
+@item arm_neon_fp16
+NEON and half-precision floating point support. Only ARM targets
+support this feature, and only then in certain modes; see
+the @ref{arm_neon_ok,,arm_neon_fp16_ok effective target keyword}.
@end table
@node Require Support