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Re: PATCH: [4.4/4.5 Regression] -fschedule-insns causes FAIL: gcc.target/i386/vararg-1.c execution test
- From: "H.J. Lu" <hjl dot tools at gmail dot com>
- To: Jan Hubicka <hubicka at ucw dot cz>
- Cc: gcc-patches at gcc dot gnu dot org, ubizjak at gmail dot com
- Date: Wed, 7 Apr 2010 06:30:16 -0700
- Subject: Re: PATCH: [4.4/4.5 Regression] -fschedule-insns causes FAIL: gcc.target/i386/vararg-1.c execution test
- References: <20100407055756.GA24319@intel.com> <20100407093324.GJ16236@atrey.karlin.mff.cuni.cz>
On Wed, Apr 7, 2010 at 2:33 AM, Jan Hubicka <email@example.com> wrote:
>> "*sse_prologue_save_insn" generates movaps on 64bit aligned memory.
>> This patch replaces movaps with movups. ?OK for trunk and 4.3/4.4/4.5
> Hmm, I guess situation is more stubble here. ?When the stack on function entry
> is aligned, the register save area will get aligned to 128bits. ?This is
> required by the ABI and used in va_arg expansion.
> So the patch is wrong. ?I guess the real issue here is that nothing in foo
> actually uses the alignemnt so we optimize the caller leaving misaligned stack
> per preferred_stack_alignment propagation?
> I guess we need to be bit cureful here - when expanding va_arg that does require alignment
> we need to bump up the alignment requirements and when doing SSE save prologue and we
> know that alignment is not needed (and thus full XMM register is never obtained) I guess
> we can end up outputing 64bit stores to optimize performance.
Please take a look at setup_incoming_varargs_64. It only aligns the
register save area
to 8 byte:
set_mem_alias_set (mem, set);
set_mem_align (mem, BITS_PER_WORD);
/* And finally do the dirty job! */
emit_insn (gen_sse_prologue_save (mem, nsse_reg,
GEN_INT (cum->sse_regno), label));