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RE: [Patch : H8300] Fix regressions for bit related instructions


>> You've got a matching constraint to force allocation/reloading 
>> to make operands 0&  1 match.  Therefore I think the check that
>> the INTVAL of operand0 being equal to the INTVAL of operand1 is 
>> redundant.  In fact, I think that check could trigger an 
>> rtl-checking since operand 0 could be (MEM (REG)) and you're not 
>> supposed to ask for INTVAL (REG).

The check for INTVAL was inserted because the compiler generated an
ICE in reloads with -O2 for msx target for following testcase,

#define MSTPCRA (*(volatile unsigned char*)0xFFFDC8)
#define MSTPCRA2 (*(volatile unsigned char*)0xFFFDB8)

int main()
   MSTPCRA = MSTPCRA2 & ~ 0x0004;
   return 0;

>> I notice that you test single_zero_operand in the insn condition 
>> in the new patterns.  Is there some reason you don't use that for
>> the appropriate operand's predicate?  It's not a big deal, but 
>> doing it that way ought to be marginally faster.
As per your suggestion, we used the single_zero_operand predicate
with matching constraints (Y0,Y2) which seems to work well. Also, 
the check for INTVAL is no longer required as the predicate seems to 
catch this at an earlier stage.

>> You have a couple define_splits that test&&  BYTES_BIG_ENDIAN.  
>> It seems to me that BYTES_BIG_ENDIAN is always true on the H8 
>> series, so I think that test is always going to be true and 
>> should simply be removed.
Yes, we will remove this check.

Please find attached the patch with the following changes,
- single_zero_operand/single_one_operand used in predicate with 
  matching constraint (Y0/Y2)
- Check for BYTES_BIG_ENDIAN removed
- Check for INTVAL of operands removed

Please comment.

Kaushik Phatak 


2010-03-10  Kaushik Phatak <>

	* config/h8300/h8300.c (print_operand) : Modify case 'V' and
	case 'W' print operands for HI mode.
	* config/h8300/h8300.h (OK_FOR_U): Support 'U' constraint for H8300SX.
	(Y0, Y2) : New constraints.
	* config/h8300/ (movqi_h8sx, movhi_h8sx, movsi_h8sx, 
	cmphi_h8300hs_znvc, cmpsi, addhi3_h8sx) : Emit instructions in #xx:3 
	and #xx:4 mode.
	(bclrqi_msx, bclrhi_msx, bsetqi_msx, bsethi_msx, bnotqi_msx,
	bnothi_msx) : New insn.
	(andqi3_2, andqi3_1, iorqi3_1, xorqi3_1) : Modify constraints to
	generate effective logical insn.
	(xorqi3) : Add support for H8300SX.
	* config/h8300/ (bit_register_indirect_operand): New Predicate.

Attachment: h8_enhancement_updated.patch
Description: h8_enhancement_updated.patch

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