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PATCH:PR target/43175: [Bug target/43175] __builtin_ia32_vec_perm_v4si doesn't work with -msse4.1
- From: "H.J. Lu" <hongjiu dot lu at intel dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Uros Bizjak <ubizjak at gmail dot com>
- Date: Thu, 25 Feb 2010 13:09:09 -0800
- Subject: PATCH:PR target/43175: [Bug target/43175] __builtin_ia32_vec_perm_v4si doesn't work with -msse4.1
- Reply-to: "H.J. Lu" <hjl dot tools at gmail dot com>
Hi,
This patch fixes 2 typos in expand_vec_perm_blend. I am testing it
on Intel Core i7. OK to install if it passes regressions.
Thanks.
H.J.
---
gcc/
2010-02-25 Uros Bizjak <ubizjak@gmail.com>
PR target/43175
* config/i386/i386.c (expand_vec_perm_blend): Use correct
operands in V8HImode subregs. Fix operand order in VEC_MERGE
rtx.
gcc/testsuite/
2010-02-25 H.J. Lu <hongjiu.lu@intel.com>
PR target/43175
* gcc.target/i386/vperm-v4si-2-sse4.c: New.
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 57c7890..f3c0c1f 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -29148,8 +29148,8 @@ expand_vec_perm_blend (struct expand_vec_perm_d *d)
do_subreg:
vmode = V8HImode;
target = gen_lowpart (vmode, target);
- op0 = gen_lowpart (vmode, target);
- op1 = gen_lowpart (vmode, target);
+ op0 = gen_lowpart (vmode, op0);
+ op1 = gen_lowpart (vmode, op1);
break;
default:
@@ -29157,7 +29157,7 @@ expand_vec_perm_blend (struct expand_vec_perm_d *d)
}
/* This matches five different patterns with the different modes. */
- x = gen_rtx_VEC_MERGE (vmode, op0, op1, GEN_INT (mask));
+ x = gen_rtx_VEC_MERGE (vmode, op1, op0, GEN_INT (mask));
x = gen_rtx_SET (VOIDmode, target, x);
emit_insn (x);
--- /dev/null 2010-02-25 11:04:09.340731622 -0800
+++ gcc-avx/gcc/testsuite/gcc.target/i386/vperm-v4si-2-sse4.c 2010-02-25 12:22:51.358069521 -0800
@@ -0,0 +1,4 @@
+/* { dg-do run } */
+/* { dg-require-effective-target sse4 } */
+/* { dg-options "-O -msse4" } */
+#include "vperm-v4si-2.c"