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ARM: Improve NEON move code
- From: Daniel Jacobowitz <drow at false dot org>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 10 Nov 2009 16:14:02 -0500
- Subject: ARM: Improve NEON move code
The NEON mov<mode> expanders will happily create RTL for (set (mem)
(const_vec)). There isn't an instruction for that, so eventually
reload punts the constant to a register. But we can get much better
code if we have the right RTL from expand time.
Tested on arm-none-eabi. OK to commit?
--
Daniel Jacobowitz
CodeSourcery
2009-11-10 Daniel Jacobowitz <dan@codesourcery.com>
* config/arm/neon.md (*neon_mov<mode>): Reject two non-register
operands.
(movti, mov<mode>): Call force_reg on one operand if required.
* config/arm/vec-common.md (mov<mode>): Likewise.
---
gcc/config/arm/neon.md | 22 +++++++++++++++++++---
gcc/config/arm/vec-common.md | 5 +++++
2 files changed, 24 insertions(+), 3 deletions(-)
Index: gcc/config/arm/vec-common.md
===================================================================
--- gcc/config/arm/vec-common.md.orig 2009-11-10 06:38:27.000000000 -0800
+++ gcc/config/arm/vec-common.md 2009-11-10 06:46:42.000000000 -0800
@@ -38,6 +38,11 @@
"TARGET_NEON
|| (TARGET_REALLY_IWMMXT && VALID_IWMMXT_REG_MODE (<MODE>mode))"
{
+ if (can_create_pseudo_p ())
+ {
+ if (GET_CODE (operands[0]) != REG)
+ operands[1] = force_reg (<MODE>mode, operands[1]);
+ }
})
;; Vector arithmetic. Expanders are blank, then unnamed insns implement
Index: gcc/config/arm/neon.md
===================================================================
--- gcc/config/arm/neon.md.orig 2009-11-10 06:40:14.000000000 -0800
+++ gcc/config/arm/neon.md 2009-11-10 06:46:42.000000000 -0800
@@ -459,7 +459,9 @@
"=w,Uv,w, w, ?r,?w,?r,?r, ?Us")
(match_operand:VD 1 "general_operand"
" w,w, Dn,Uvi, w, r, r, Usi,r"))]
- "TARGET_NEON"
+ "TARGET_NEON
+ && (register_operand (operands[0], <MODE>mode)
+ || register_operand (operands[1], <MODE>mode))"
{
if (which_alternative == 2)
{
@@ -506,7 +508,9 @@
"=w,Un,w, w, ?r,?w,?r,?r, ?Us")
(match_operand:VQXMOV 1 "general_operand"
" w,w, Dn,Uni, w, r, r, Usi, r"))]
- "TARGET_NEON"
+ "TARGET_NEON
+ && (register_operand (operands[0], <MODE>mode)
+ || register_operand (operands[1], <MODE>mode))"
{
if (which_alternative == 2)
{
@@ -549,6 +553,11 @@
(match_operand:TI 1 "general_operand" ""))]
"TARGET_NEON"
{
+ if (can_create_pseudo_p ())
+ {
+ if (GET_CODE (operands[0]) != REG)
+ operands[1] = force_reg (TImode, operands[1]);
+ }
})
(define_expand "mov<mode>"
@@ -556,12 +565,19 @@
(match_operand:VSTRUCT 1 "general_operand" ""))]
"TARGET_NEON"
{
+ if (can_create_pseudo_p ())
+ {
+ if (GET_CODE (operands[0]) != REG)
+ operands[1] = force_reg (<MODE>mode, operands[1]);
+ }
})
(define_insn "*neon_mov<mode>"
[(set (match_operand:VSTRUCT 0 "nonimmediate_operand" "=w,Ut,w")
(match_operand:VSTRUCT 1 "general_operand" " w,w, Ut"))]
- "TARGET_NEON"
+ "TARGET_NEON
+ && (register_operand (operands[0], <MODE>mode)
+ || register_operand (operands[1], <MODE>mode))"
{
switch (which_alternative)
{