RFA: Add support for Renesas RX architectiure to GCC

[Nick Clifton <nickc at redhat dot com>]

Hi Guys,

  On behalf of Red Hat I would like contribute support for a new
  processor architecture to GCC.  This is for the Renesas RX cpu,
  details of which can be found here:

http://eu.renesas.com/fmwk.jsp?cnt=rx600_series_landing.jsp&fp=/products/mpumcu/rx_family/rx600_series
http://documentation.renesas.com/eng/products/mpumcu/rej09b0460_rx610hm.pdf

  The port builds without any problems, although if this patch is
  accepted I do intend to submit a follow up patch to tweak some of
  the tests in the gcc testsuite.
  
  I am also volunteering to act as the maintainer for this port.

  OK to apply ?

Cheers
  Nick

./ChangeLog
2009-09-30  Nick Clifton  <nickc@redhat.com>

	* MAINTAINERS: Add myself as a maintainer for the RX.

gcc/ChangeLog

        * config.gcc: Add rx-elf target.
        * doc/extend.texi: Document RX function attributes and
	built-in functions.
        * doc/invoke.texi: Document RX specific command line
	switches.
        * config/rx: New directory.
        * config/rx/constraints.md: New file.
        * config/rx/predicates.md: New file.
        * config/rx/rx-abi-functions.c: New file.
        * config/rx/rx-abi.h: New file.
        * config/rx/rx.c: New file.
        * config/rx/rx.h: New file.
        * config/rx/rx.md: New file.
        * config/rx/rx.opt: New file.
        * config/rx/rx-protos.h: New file.
        * config/rx/t-rx: New file.

libgcc/ChangeLog

        * config.host: Add rx-elf target.

Index: gcc/doc/extend.texi
===================================================================
--- gcc/doc/extend.texi	(revision 152326)
+++ gcc/doc/extend.texi	(working copy)
@@ -2244,6 +2244,13 @@
 You must use GAS and GLD from GNU binutils version 2.7 or later for
 this attribute to work correctly.
 
+@item exception
+@cindex exception handler functions on the RX processor
+Use this attribute on the RX to indicate that the specified function
+is an exception handler.  The compiler will generate function entry and
+exit sequences suitable for use in an exception handler when this
+attribute is present.
+
 @item exception_handler
 @cindex exception handler functions on the Blackfin processor
 Use this attribute on the Blackfin to indicate that the specified function
@@ -2280,7 +2287,7 @@
 
 @item fast_interrupt
 @cindex interrupt handler functions
-Use this attribute on the M32C port to indicate that the specified
+Use this attribute on the M32C and RX ports to indicate that the specified
 function is a fast interrupt handler.  This is just like the
 @code{interrupt} attribute, except that @code{freit} is used to return
 instead of @code{reit}.
@@ -2472,8 +2479,8 @@
 
 @item interrupt
 @cindex interrupt handler functions
-Use this attribute on the ARM, AVR, CRX, M32C, M32R/D, m68k, MeP, MIPS
-and Xstormy16 ports to indicate that the specified function is an
+Use this attribute on the ARM, AVR, CRX, M32C, M32R/D, m68k, MeP, MIPS,
+RX and Xstormy16 ports to indicate that the specified function is an
 interrupt handler.  The compiler will generate function entry and exit
 sequences suitable for use in an interrupt handler when this attribute
 is present.
@@ -2681,7 +2688,7 @@
 
 @item naked
 @cindex function without a prologue/epilogue code
-Use this attribute on the ARM, AVR, IP2K and SPU ports to indicate that
+Use this attribute on the ARM, AVR, IP2K, RX and SPU ports to indicate that
 the specified function does not need prologue/epilogue sequences generated by
 the compiler.  It is up to the programmer to provide these sequences. The 
 only statements that can be safely included in naked functions are 
@@ -7452,6 +7459,7 @@
 * Other MIPS Built-in Functions::
 * picoChip Built-in Functions::
 * PowerPC AltiVec/VSX Built-in Functions::
+* RX Built-in Functions::
 * SPARC VIS Built-in Functions::
 * SPU Built-in Functions::
 @end menu
@@ -11746,6 +11754,185 @@
 int __builtin_bswap16 (int);
 @end smallexample
 
+@node RX Built-in Functions
+@subsection RX Built-in Functions
+GCC supports some of the RX instructions which cannot be expressed in
+the C programming language via the use of built-in functions.  The
+following functions are supported:
+
+@table @code
+
+@item int __builtin_rx_adc (int, int)
+Generates the @code{adc} machine instruction which adds the two
+arguments together along with the value in the carry flag.
+
+@item int __builtin_rx_bm<cnd> (int word, int bit)
+Generates the @code{bm} machine instruction which sets or clears the
+indicated bit in the indicated word based on the status of the
+@code{<cnd>} condition.  Permited values for @code{<cnd>} are:
+@samp{eq, ne, gt, ge, lt, le, gtu, geu, ltu, leu, pz, n, o, no}.
+
+@item void __builtin_rx_brk (void)
+Generates the @code{brk} machine instruction.
+
+@item void __builtin_rx_btst (int word, int bit)
+Generates the @code{btst} machine instruction which sets the Z and C
+condition code flags in the processor status word based on the
+specified bit in the specified word.
+
+@item void __builtin_rx_clrpsw (int)
+Generates the @code{clrpsw} machine instruction to clear the specified
+bit in the processor status word.
+
+@item void __builtin_rx_int (int)
+Generates the @code{int} machine instruction to generate an interrupt
+with the specified value.
+
+@item void __builtin_rx_machi (int, int)
+Generates the @code{machi} machine instruction to add the result of
+multiplying the top 16-bits of the two arguments into the
+accumulator.
+
+@item void __builtin_rx_maclo (int, int)
+Generates the @code{maclo} machine instruction to add the result of
+multiplying the bottom 16-bits of the two arguments into the
+accumulator.
+
+@item void __builtin_rx_mulhi (int, int)
+Generates the @code{mulhi} machine instruction to place the result of
+multiplying the top 16-bits of the two arguments into the
+accumulator.
+
+@item void __builtin_rx_mullo (int, int)
+Generates the @code{mullo} machine instruction to place the result of
+multiplying the bottom 16-bits of the two arguments into the
+accumulator.
+
+@item int  __builtin_rx_mvfachi (void)
+Generates the @code{mvfachi} machine instruction to read the top
+32-bits of the accumulator.
+
+@item int  __builtin_rx_mvfacmi (void)
+Generates the @code{mvfacmi} machine instruction to read the middle
+32-bits of the accumulator.
+
+@item int __builtin_rx_mvfc (int)
+Generates the @code{mvfc} machine instruction which reads the control
+register specified in its argument and returns its value.
+
+@c @item int __builtin_rx_mvfcp (int cpnum, int cpreg)
+@c Generates the @code{mvcfp} machine instruction which returns the
+@c contents of co-processor number @code{cpnum}'s register number
+@c @code{cpreg}.
+
+@item void __builtin_rx_mvtachi (int)
+Generates the @code{mvtachi} machine instruction to set the top
+32-bits of the accumulator.
+
+@item void __builtin_rx_mvtaclo (int)
+Generates the @code{mvtaclo} machine instruction to set the bottom
+32-bits of the accumulator.
+
+@item void __builtin_rx_mvtc (int reg, int val)
+Generates the @code{mvtc} machine instruction which sets control
+register number @code{reg} to @code{val}.
+
+@c @item void __builtin_rx_mvtcp (int cpnum, int cpreg, int val)
+@c Generates the @code{mvtcp} machine instruction which sets register
+@c number @code{cpreg} of co-processor @code{cpnum} to @code{val}.
+
+@item void __builtin_rx_mvtipl (int)
+Generates the @code{mvtipl} machine instruction set the interrupt
+priority level.
+
+@c @item void __builtin_rx_opecp (int cpnum, int cpopcode)
+@c Generates the @code{opecp} machine instruction which instructions
+@c co-processor @code{cpnum} to perform operation @code{cpopcode}.
+
+@item void __builtin_rx_popc (int)
+Generates the @code{popc} machine instruction to pop the specified
+control register off the stack.
+
+@item void __builtin_rx_pushc (int)
+Generates the @code{pushc} machine instruction to push the specified
+control register onto the stack.
+
+@item void __builtin_rx_racw (int)
+Generates the @code{racw} machine instruction to round the accumulator
+according to the specified mode.
+
+@item int __builtin_rx_revl (int)
+Generates the @code{revl} machine instruction which swaps the bytes in
+the argument so that the least significant 8 bits now occupy bits 24
+to 31 and so on.
+
+@item int __builtin_rx_revw (int)
+Generates the @code{revw} machine instruction which swaps the bytes in
+the argument so that bits 0-7 now occupy bits 8-15 and vice versa, and
+also bits 16-23 occupy bits 24-31 and vice versa.
+
+@item void __builtin_rx_rmpa (void)
+Generates the @code{rmpa} machine instruction which initiates a
+repeated multiply and accumulate sequence.
+
+@item int __builtin_rx_rolc (int)
+Generates the @code{rolc} machine instruction which returns the
+argument rotated left by one bit through the carry flag.
+
+@item int __builtin_rx_rorc (int)
+Generates the @code{rorc} machine instruction which returns the
+argument rotated right by one bit through the carry flag.
+
+@item void __builtin_rx_round (float)
+Generates the @code{round} machine instruction which returns the
+floating point argument rounded according to the current rounding mode
+set in the floating point status word register.
+
+@item int __builtin_rx_sat (int)
+Generates the @code{sat} machine instruction which returns the
+saturated value of the argument.
+
+@item void __builtin_rx_satr (void)
+Generates the @code{satr} machine instruction which performs a 64-bit
+saturate operation on the registers used by the @code{rmpa}
+instruction.
+
+@item int __builtin_rx_sbb (int left, int right)
+Generates the @code{sbb} machine instruction which subtracts
+@code{right} from @code{left}, including a borrow from the carry flag.
+
+@item int __builtin_rx_sc<cnd> (void)
+Generates the @code{sc} machine instruction to restrieve the specified
+truth condition from the condition code flags.  Permited values for
+@code{<cnd>} are: @samp{eq, ne, gt, ge, lt, le, gtu, geu, ltu, leu,
+pz, n, o, no}.
+
+@item void __builtin_rx_setpsw (int)
+Generates the @code{setpsw} machine instruction to set the specified
+bit in the processor status word.
+
+@item int __builtin_rx_stnz (int)
+Generates the @code{stnz} machine instruction to return the specified
+value if the Z flag in the processor status word is clear.
+
+@item int __builtin_rx_stz (int)
+Generates the @code{stz} machine instruction to return the specified
+value if the Z flag in the processor status word is set.
+
+@item void __builtin_rx_tst (int, int)
+Generates the @code{tst} machine instruction which sets the Z and C
+condition code flags in the processor status word based on the result
+of performing a bitwise AND operator between the two arguments.
+
+@item void __builtin_rx_wait (void)
+Generates the @code{wait} machine instruction.
+
+@item void __builtin_rx_xchg (int *, int)
+Generates the @code{xchg} machine instruction which swaps the two
+arguments.
+
+@end table
+
 @node SPARC VIS Built-in Functions
 @subsection SPARC VIS Built-in Functions
 
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi	(revision 152326)
+++ gcc/doc/invoke.texi	(working copy)
@@ -781,6 +781,16 @@
 -msim  -mmvme  -mads  -myellowknife  -memb  -msdata @gol
 -msdata=@var{opt}  -mvxworks  -G @var{num}  -pthread}
 
+@emph{RX Options}
+@gccoptlist{-m64bit-doubles  -m32bit-doubles  -mieee  -mno-ieee@gol
+-mbig-endian-data -mlittle-endian-data @gol
+-msmall-data @gol
+-msim  -mno-sim@gol
+-mas100-syntax -mno-as100-syntax@gol
+-mrelax@gol
+-mmax-constant-size=@gol
+-mint-register=}
+
 @emph{S/390 and zSeries Options}
 @gccoptlist{-mtune=@var{cpu-type}  -march=@var{cpu-type} @gol
 -mhard-float  -msoft-float  -mhard-dfp -mno-hard-dfp @gol
@@ -9268,6 +9278,7 @@
 * picoChip Options::
 * PowerPC Options::
 * RS/6000 and PowerPC Options::
+* RX Options::
 * S/390 and zSeries Options::
 * Score Options::
 * SH Options::
@@ -15104,6 +15115,116 @@
 
 @end table
 
+@node RX Options
+@subsection RX Options
+@cindex RX Options
+
+These @option{-m} options are defined for RX implementations:
+
+@table @gcctabopt
+@item -m64bit-doubles
+@itemx -m32bit-doubles
+@itemx -mieee
+@itemx -mno-ieee
+@opindex m64bit-doubles
+@opindex m32bit-doubles
+@opindex mieee
+@opindex mno-ieee
+Make the @code{double} data type be 64-bits (@option{-m64bit-doubles})
+or 32-bits (@option{-m32bit-doubles}) in size.  The default is
+@option{-m32bit-doubles}.  For IEEE-754 compliance 64-bit doubles are
+needed.  @emph{Note} in addition the use of the RX floating point
+instructions is only enabled when @option{-m32bit-doubles} is in force.
+This is because the RX instructions do not properly support denormal
+(or sub-normal) values.  Hence the command line option @option{-mieee}
+is an alias for @option{-m64bit-doubles} and the command line option
+@option{-mno-ieee} is an alias for @option{-m32bit-doubles}.
+
+@item -mbig-endian-data
+@itemx -mlittle-endian-data
+@opindex mbig-endian-data
+@opindex mlittle-endian-data
+Store data (but not code) in the big-endian format.  The default is
+@option{-mlittle-endian-data}, ie to store data in the little endian
+format.
+
+@item -msmall-data-limit=@var{N}
+@opindex msmall-data-limit
+Specifies the maximum size in bytes of global and static variables
+which can be placed into the small data area.  Using the small data
+area can lead to smaller and faster code, but the size of area is
+limited and it is up to the programmer to ensure that the area does
+not overflow.  Also when the small data area is used one of the RX's
+registers (r13) is reserved for use pointing to this area, so it is no
+longer available for use by the compiler.  This could result in slower
+and/or larger code if variables which once could have been held in r13
+are now pushed onto the stack.
+
+Note, common variables (variables which have not been initialised) and
+constants are not placed into the small data area as they are assigned
+to other sections in the output executeable.
+
+The default value is zero, which disables this feature.  Note, this
+feature is not enabled by default with higher optimization levels
+(@option{-O2} etc) because of the potentially deterimental effects of
+reserving register r13.  It is up to the programmer to experiment and
+discover whether this feature is of benefit to their program.
+
+@item -msim
+@item -mno-sim
+@opindex msim
+@opindex mno-sim
+Use the simulator runtime.  The default is to use the libgloss board
+specific runtime.
+
+@item -mas100-syntax
+@item -mno-as100-syntax
+@opindex mas100-syntax
+@opindex mno-as100-syntax
+When generating assembler output use a syntax that is compatible with
+Renesas's AS100 assembler.  This syntax can also be handled by the GAS
+assembler but it has some restrictions so generating it is not the
+default option.
+
+@item -mmax-constant-size=@var{N}
+@opindex mmax-constant-size
+Specifies the maxium size, in bytes, of a constant that can be used as
+an operand in a RX instruction.  Although the RX instruction set does
+allow consants of up to 4 bytes in length to be used in instructions,
+a longer value equates to a longer instruction.  Thus in some
+circumstances it can be beneficial to restrict the size of constants
+that are used in instructions.  Constants that are too big are instead
+placed into a constant pool and referenced via register indirection.
+
+The value @var{N} can be between 0 and 3.  A value of 0, the default,
+means that constants of any size are allowed.
+
+@item -mrelax
+@opindex mrelax
+Enable linker relaxation.  Linker relaxation is a process whereby the
+linker will attempt to reduce the size of a program by finding shorter
+versions of various instructions.  Disabled by default.
+
+@item -mint-register=@var{N}
+@opindex mint-register
+Specify the number of registers to reserve for fast interrupt handler
+functions.  The value @var{N} can be between 0 and 4.  A value of 1
+means that register r13 will be reserved for ther exclusive use of
+fast interrupt handlers.  A value of 2 reserves r13 and r12.  A value
+of 3 reserves r13, r12 and r11, and a value of 4 reserves r13 through
+r10.  A value of 0, the default, does not reserve any registers.
+@end table
+
+@emph{Note:} The generic GCC command line @option{-ffixed-@var{reg}}
+has special significance to the RX port when used with the
+@code{interrupt} function attribute.  This attribute indicates a
+function intended to process fast interrupts.  GCC will will ensure
+that it only uses the registers @code{r10}, @code{r11}, @code{r12}
+and/or @code{r13} and only provided that the normal use of the
+corresponding registers have been restricted via the
+@option{-ffixed-@var{reg}} or @option{-mint-register} command line
+options.
+
 @node S/390 and zSeries Options
 @subsection S/390 and zSeries Options
 @cindex S/390 and zSeries Options
Index: gcc/config.gcc
===================================================================
--- gcc/config.gcc	(revision 152326)
+++ gcc/config.gcc	(working copy)
@@ -2077,6 +2077,10 @@
 	use_gcc_stdint=wrap
 	extra_headers=altivec.h
 	;;
+rx-*-elf*)
+	tm_file="dbxelf.h elfos.h svr4.h newlib-stdint.h ${tm_file} rx/rx-abi.h"
+	tmake_file="${tmake_file} rx/t-rx"
+	;;
 s390-*-linux*)
 	tm_file="s390/s390.h dbxelf.h elfos.h svr4.h linux.h glibc-stdint.h s390/linux.h"
 	tmake_file="${tmake_file} t-dfprules s390/t-crtstuff s390/t-linux"
Index: libgcc/config.host
===================================================================
--- libgcc/config.host	(revision 152326)
+++ libgcc/config.host	(working copy)
@@ -482,6 +482,9 @@
 	;;
 rs6000-ibm-aix[56789].* | powerpc-ibm-aix[56789].*)
 	;;
+rx-*-elf)
+	extra_parts="crtbegin.o crtend.o"
+	;;
 s390-*-linux*)
 	;;
 s390x-*-linux*)
Index: MAINTAINERS
===================================================================
--- MAINTAINERS	(revision 152323)
+++ MAINTAINERS	(working copy)
@@ -82,6 +82,7 @@
 rs6000 port		Geoff Keating		geoffk@geoffk.org
 rs6000 port		David Edelsohn		edelsohn@gnu.org
 rs6000 vector extns	Aldy Hernandez		aldyh@redhat.com
+rx port	      		Nick Clifton		nickc@redhat.com
 s390 port		Hartmut Penner		hpenner@de.ibm.com
 s390 port		Ulrich Weigand		uweigand@de.ibm.com
 s390 port		Andreas Krebbel		Andreas.Krebbel@de.ibm.com

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