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Re: [PATCH] MIPS: Optimize atomic memory operations for TARGET_OCTEON.


David Daney wrote:
This is a follow up to an uncommitted patch I send over a month ago. For the Octeon processor, we can use the SYNCW instruction instead of SYNC in some situations for increased performance.

On Octeon the combination SYNCW ... other instructions ... SC functions as a full memory barrier and is faster than the same sequence written with a SYNC.

After Richard's rewrite of the atomic memory RTL expanders, this patch becomes almost trivial, we gate the use of SYNCW on TARGET_OCTEON.

Other places we emit SYNC are not followed by SC, so the optimization does not apply there.


Tested on mips64-unknown-linux-gnu all default languages and RUNTESTFLAGS="--target_board=unix/\{,-mabi=64\}" with no regressions.



For completeness, I should also probably add the I configured with --with-float=soft --with-arch=octeon.


David Daney


OK to commit?

2009-09-29 David Daney <ddaney@caviumnetworks.com>

    * gcc/config/mips/mips.c (mips_process_sync_loop) Emit syncw
    instructions for TARGET_OCTEON.



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