[PATCH] Powerpc patch #4, Add power7/vsx support

[Michael Meissner <meissner at linux dot vnet dot ibm dot com>]

This patch adds support for the powerpc ISA 2.06 instruction set which includes
support for the new VSX instruction set, and scheduling information for the
power7 processor.  It also adds support to vectorize some of the math builtin
functions.

This contains everything on the power7-meissner branch as of July 23rd, except
for the hack that I had put in to disable using branch on count instructions in
functions that have a switch statement or indirect jump, which papered over a
bug where the compiler tried to swap a floating point register to the LR
register in one of the spec 2006 benchmarks.

I also didn't put in the changes to make -mspe and -mpaired back to being
target bitmask options, which elimianates a long standing hack in the
compiler (basically we ran out of bits for target options, so spe/paired became
separate variables, which was awkward for builtin functions).  I will submit
this as a separate patch after I've tested it further.

One unresolved thing is how the compiler should mark the VSX registers in the
debug output.  Do we need to use a separate register number for VSX registers,
or do we reuse the existing FPR and Altivec register numbers (which is what the
code currently does).

When I submitted the bswap changes, I had forgotten to submit several of the
tests, and those are submitted here.

In addition to make check, I just built spec 2006, and all 29 benchmarks build
and validate (18 of the 29 benchmarks generate vector double instructions).

Are these patches ok to commit?

-- 
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meissner@linux.vnet.ibm.com

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