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[PATCH] SH: Add documents for -m2a* option
- From: Takashi Yoshii <yoshii dot takashi at renesas dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: kkojima at gcc dot gnu dot org
- Date: Tue, 23 Jun 2009 18:45:14 +0900
- Subject: [PATCH] SH: Add documents for -m2a* option
# This is bug #40515. Sorry, but I don't know how to link ML and BTS.
On SH cpu, sh2a and its valiants have been supported since r85286.
But -m2a, -m2a-single, -m2a-single-only and -m2a-nofpu options found
in gcc/config/sh/sh.opt are not documented in the manual.
This patch also try to clarify that -m2a* other than -m2a-nofpu generates
SH2A-FPU code, because I found people are confused by -m2a option.
I guess it is partly because Gcc's option {-m2a, -m2a-nofpu}
corresponds to Manufacturer's CPU class {SH2A-FPU, SH-2A}.
BTW.
Anyone know why the manual uses lower case suffix like SH4a but SH-4A?
This time I followed the rule without knowing why.
Possibly "(R)" avoidance?
/yoshii
2009-06-23 Takashi YOSHII <yoshii.takashi@renesas.com>
* doc/invoke.texi (SH Options): Document -m2a, -m2a-single
-m2a-single-only and -m2a-nofpu.
* gcc/config/sh.opt: Document m2a generates FPU code.
Index: gcc/doc/invoke.texi
===================================================================
--- gcc/doc/invoke.texi (revision 148828)
+++ gcc/doc/invoke.texi (working copy)
@@ -778,7 +778,9 @@
-mscore5 -mscore5u -mscore7 -mscore7d}
@emph{SH Options}
-@gccoptlist{-m1 -m2 -m2e -m3 -m3e @gol
+@gccoptlist{-m1 -m2 -m2e @gol
+-m2a-nofpu -m2a-single-only -m2a-single -m2a @gol
+-m3 -m3e @gol
-m4-nofpu -m4-single-only -m4-single -m4 @gol
-m4a-nofpu -m4a-single-only -m4a-single -m4a -m4al @gol
-m5-64media -m5-64media-nofpu @gol
@@ -14934,6 +14936,26 @@
@item -m2e
Generate code for the SH2e.
+@item -m2a-nofpu
+@opindex m2a-nofpu
+Generate code for the SH2a without FPU, or for a SH2a-FPU in such a way
+that the floating-point unit is not used.
+
+@item -m2a-single-only
+@opindex m2a-single-only
+Generate code for the SH2a-FPU, in such a way that no double-precision
+floating point operations are used.
+
+@item -m2a-single
+@opindex m2a-single
+Generate code for the SH2a-FPU assuming the floating-point unit is in
+single-precision mode by default.
+
+@item -m2a
+@opindex m2a
+Generate code for the SH2a-FPU assuming the floating-point unit is in
+double-precision mode by default.
+
@item -m3
@opindex m3
Generate code for the SH3.
Index: gcc/config/sh/sh.opt
===================================================================
--- gcc/config/sh/sh.opt (revision 148828)
+++ gcc/config/sh/sh.opt (working copy)
@@ -49,7 +49,7 @@
m2a
Target RejectNegative Condition(SUPPORT_SH2A)
-Generate SH2a code
+Generate default double-precision SH2a-FPU code
m2a-nofpu
Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
@@ -57,11 +57,11 @@
m2a-single
Target RejectNegative Condition(SUPPORT_SH2A_SINGLE)
-Generate default single-precision SH2a code
+Generate default single-precision SH2a-FPU code
m2a-single-only
Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY)
-Generate only single-precision SH2a code
+Generate only single-precision SH2a-FPU code
m2e
Target RejectNegative Condition(SUPPORT_SH2E)