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Re: PATCH: PR target/40470: unabl e to find a register to spill in class ‘SSE_FIRST_REG’

H.J. Lu wrote:
On Wed, Jun 17, 2009 at 11:18 AM, Vladimir Makarov<> wrote:
I am agree with Jeff and Richard. There is one more reason to avoid using
hard registers. Usage of hard registers tends to create more spill failures
in reload.

It is not like you have a choice here. The register for those insns is fixed. Sooner or later you have to allocate xmm0 for them.

This is one simple example when usage a hard register could degrade performance.

h0<-... (insn which has one alternative requiring a particular hard register h0)



You can not use h0 in the loop if it is very hungry for registers like h0. If you used pseudo p0 instead of h0, IRA could spill p0 (put it int memory after the 1st insn) and restore it after the loop.

So I'd never use hard register even in insn using only it. Using hard register also might result (through copy propagation) in even more hard register usage in insns and most of them do not require a particular hard register. So the problem I mentioned above would escalate more.

I will open a bug where gcc generates inefficient code when
hard register isn't used early.

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