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[power7-meissner] Fix bswaphi; Make test divide/sqrt instructions match the hardware
- From: Michael Meissner <meissner at linux dot vnet dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 16 Jun 2009 19:12:10 -0400
- Subject: [power7-meissner] Fix bswaphi; Make test divide/sqrt instructions match the hardware
This patch fixes the issue with bswaphi that Richard Henderson pointed out. It
also changes the support the for test divide and test sqrt instructions to
match the hardware, but setting a condition code register. The functions are
split into two builtins, one that looks at the FG (greater than) flag and one
that looks at the FE (equal) flag.
[gcc]
2009-06-16 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (bdesc_2arg): Split tdiv/tsqrt patterns
into 2 separate patterns, one that returns the FE flag and one
that returns FG.
(bdesc_1arg): Ditto.
* config/rs6000/vsx.md (vsx_tdiv<mode>3*): Reimplment tdiv/tsqrt
patterns to match the hardware which sets a CR register based on
the inputs, not a vector register. Since two flags are set,
provide two separate patterns that returns each flag. If the
instruction is used in a test, it will be optimized to use the
normal conditional branch.
(vsx_tsqrt<mode>2*): Ditto.
* config/rs6000/rs6000.h (VSX_BUILTIN_*): Split tdiv/tsqrt
patterns into 2 separate patterns, one that returns the FE flag
and one that returns FG.
* config/rs6000/rs6000.md (bswaphi): Use HImode for force_reg
call.
[gcc/testsuite]
2009-06-16 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vsx-builtin-6.c: New file to test the divide
and sqrt test instructions.
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 148504)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -8469,7 +8469,8 @@ static struct builtin_description bdesc_
{ MASK_VSX, CODE_FOR_divv2df3, "__builtin_vsx_xvdivdp", VSX_BUILTIN_XVDIVDP },
{ MASK_VSX, CODE_FOR_sminv2df3, "__builtin_vsx_xvmindp", VSX_BUILTIN_XVMINDP },
{ MASK_VSX, CODE_FOR_smaxv2df3, "__builtin_vsx_xvmaxdp", VSX_BUILTIN_XVMAXDP },
- { MASK_VSX, CODE_FOR_vsx_tdivv2df3, "__builtin_vsx_xvtdivdp", VSX_BUILTIN_XVTDIVDP },
+ { MASK_VSX, CODE_FOR_vsx_tdivv2df3_fe, "__builtin_vsx_xvtdivdp_fe", VSX_BUILTIN_XVTDIVDP_FE },
+ { MASK_VSX, CODE_FOR_vsx_tdivv2df3_fg, "__builtin_vsx_xvtdivdp_fg", VSX_BUILTIN_XVTDIVDP_FG },
{ MASK_VSX, CODE_FOR_vector_eqv2df, "__builtin_vsx_xvcmpeqdp", VSX_BUILTIN_XVCMPEQDP },
{ MASK_VSX, CODE_FOR_vector_gtv2df, "__builtin_vsx_xvcmpgtdp", VSX_BUILTIN_XVCMPGTDP },
{ MASK_VSX, CODE_FOR_vector_gev2df, "__builtin_vsx_xvcmpgedp", VSX_BUILTIN_XVCMPGEDP },
@@ -8480,13 +8481,16 @@ static struct builtin_description bdesc_
{ MASK_VSX, CODE_FOR_divv4sf3, "__builtin_vsx_xvdivsp", VSX_BUILTIN_XVDIVSP },
{ MASK_VSX, CODE_FOR_sminv4sf3, "__builtin_vsx_xvminsp", VSX_BUILTIN_XVMINSP },
{ MASK_VSX, CODE_FOR_smaxv4sf3, "__builtin_vsx_xvmaxsp", VSX_BUILTIN_XVMAXSP },
- { MASK_VSX, CODE_FOR_vsx_tdivv4sf3, "__builtin_vsx_xvtdivsp", VSX_BUILTIN_XVTDIVSP },
+ { MASK_VSX, CODE_FOR_vsx_tdivv4sf3_fe, "__builtin_vsx_xvtdivsp_fe", VSX_BUILTIN_XVTDIVSP_FE },
+ { MASK_VSX, CODE_FOR_vsx_tdivv4sf3_fg, "__builtin_vsx_xvtdivsp_fg", VSX_BUILTIN_XVTDIVSP_FG },
{ MASK_VSX, CODE_FOR_vector_eqv4sf, "__builtin_vsx_xvcmpeqsp", VSX_BUILTIN_XVCMPEQSP },
{ MASK_VSX, CODE_FOR_vector_gtv4sf, "__builtin_vsx_xvcmpgtsp", VSX_BUILTIN_XVCMPGTSP },
{ MASK_VSX, CODE_FOR_vector_gev4sf, "__builtin_vsx_xvcmpgesp", VSX_BUILTIN_XVCMPGESP },
{ MASK_VSX, CODE_FOR_smindf3, "__builtin_vsx_xsmindp", VSX_BUILTIN_XSMINDP },
{ MASK_VSX, CODE_FOR_smaxdf3, "__builtin_vsx_xsmaxdp", VSX_BUILTIN_XSMAXDP },
+ { MASK_VSX, CODE_FOR_vsx_tdivdf3_fe, "__builtin_vsx_xstdivdp_fe", VSX_BUILTIN_XSTDIVDP_FE },
+ { MASK_VSX, CODE_FOR_vsx_tdivdf3_fg, "__builtin_vsx_xstdivdp_fg", VSX_BUILTIN_XSTDIVDP_FG },
{ MASK_VSX, CODE_FOR_vsx_concat_v2df, "__builtin_vsx_concat_2df", VSX_BUILTIN_CONCAT_2DF },
{ MASK_VSX, CODE_FOR_vsx_concat_v2di, "__builtin_vsx_concat_2di", VSX_BUILTIN_CONCAT_2DI },
@@ -8932,19 +8936,23 @@ static struct builtin_description bdesc_
{ MASK_VSX, CODE_FOR_negv2df2, "__builtin_vsx_xvnegdp", VSX_BUILTIN_XVNEGDP },
{ MASK_VSX, CODE_FOR_sqrtv2df2, "__builtin_vsx_xvsqrtdp", VSX_BUILTIN_XVSQRTDP },
{ MASK_VSX, CODE_FOR_vsx_rsqrtev2df2, "__builtin_vsx_xvrsqrtedp", VSX_BUILTIN_XVRSQRTEDP },
- { MASK_VSX, CODE_FOR_vsx_tsqrtv2df2, "__builtin_vsx_xvtsqrtdp", VSX_BUILTIN_XVTSQRTDP },
+ { MASK_VSX, CODE_FOR_vsx_tsqrtv2df2_fe, "__builtin_vsx_xvtsqrtdp_fe", VSX_BUILTIN_XVTSQRTDP_FE },
+ { MASK_VSX, CODE_FOR_vsx_tsqrtv2df2_fg, "__builtin_vsx_xvtsqrtdp_fg", VSX_BUILTIN_XVTSQRTDP_FG },
{ MASK_VSX, CODE_FOR_vsx_frev2df2, "__builtin_vsx_xvredp", VSX_BUILTIN_XVREDP },
{ MASK_VSX, CODE_FOR_negv4sf2, "__builtin_vsx_xvnegsp", VSX_BUILTIN_XVNEGSP },
{ MASK_VSX, CODE_FOR_sqrtv4sf2, "__builtin_vsx_xvsqrtsp", VSX_BUILTIN_XVSQRTSP },
{ MASK_VSX, CODE_FOR_vsx_rsqrtev4sf2, "__builtin_vsx_xvrsqrtesp", VSX_BUILTIN_XVRSQRTESP },
- { MASK_VSX, CODE_FOR_vsx_tsqrtv4sf2, "__builtin_vsx_xvtsqrtsp", VSX_BUILTIN_XVTSQRTSP },
+ { MASK_VSX, CODE_FOR_vsx_tsqrtv4sf2_fe, "__builtin_vsx_xvtsqrtsp_fe", VSX_BUILTIN_XVTSQRTSP_FE },
+ { MASK_VSX, CODE_FOR_vsx_tsqrtv4sf2_fg, "__builtin_vsx_xvtsqrtsp_fg", VSX_BUILTIN_XVTSQRTSP_FG },
{ MASK_VSX, CODE_FOR_vsx_frev4sf2, "__builtin_vsx_xvresp", VSX_BUILTIN_XVRESP },
{ MASK_VSX, CODE_FOR_vsx_xscvdpsp, "__builtin_vsx_xscvdpsp", VSX_BUILTIN_XSCVDPSP },
{ MASK_VSX, CODE_FOR_vsx_xscvdpsp, "__builtin_vsx_xscvspdp", VSX_BUILTIN_XSCVSPDP },
{ MASK_VSX, CODE_FOR_vsx_xvcvdpsp, "__builtin_vsx_xvcvdpsp", VSX_BUILTIN_XVCVDPSP },
{ MASK_VSX, CODE_FOR_vsx_xvcvspdp, "__builtin_vsx_xvcvspdp", VSX_BUILTIN_XVCVSPDP },
+ { MASK_VSX, CODE_FOR_vsx_tsqrtdf2_fe, "__builtin_vsx_xstsqrtdp_fe", VSX_BUILTIN_XSTSQRTDP_FE },
+ { MASK_VSX, CODE_FOR_vsx_tsqrtdf2_fg, "__builtin_vsx_xstsqrtdp_fg", VSX_BUILTIN_XSTSQRTDP_FG },
{ MASK_VSX, CODE_FOR_vsx_fix_truncv2dfv2di2, "__builtin_vsx_xvcvdpsxds", VSX_BUILTIN_XVCVDPSXDS },
{ MASK_VSX, CODE_FOR_vsx_fixuns_truncv2dfv2di2, "__builtin_vsx_xvcvdpuxds", VSX_BUILTIN_XVCVDPUXDS },
Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md (revision 148504)
+++ gcc/config/rs6000/vsx.md (working copy)
@@ -393,13 +393,41 @@ (define_insn "*vsx_div<mode>3"
[(set_attr "type" "<VStype_div>")
(set_attr "fp_type" "<VSfptype_div>")])
-(define_insn "vsx_tdiv<mode>3"
- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")]
- UNSPEC_VSX_TDIV))]
+;; *tdiv* instruction returning the FG flag
+(define_expand "vsx_tdiv<mode>3_fg"
+ [(set (match_dup 3)
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")
+ (match_operand:VSX_B 2 "vsx_register_operand" "")]
+ UNSPEC_VSX_TDIV))
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (gt:SI (match_dup 3)
+ (const_int 0)))]
+ "VECTOR_UNIT_VSX_P (<MODE>mode)"
+{
+ operands[3] = gen_reg_rtx (CCFPmode);
+})
+
+;; *tdiv* instruction returning the FE flag
+(define_expand "vsx_tdiv<mode>3_fe"
+ [(set (match_dup 3)
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")
+ (match_operand:VSX_B 2 "vsx_register_operand" "")]
+ UNSPEC_VSX_TDIV))
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (eq:SI (match_dup 3)
+ (const_int 0)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "x<VSv>tdiv<VSs> %x0,%x1,%x2"
+{
+ operands[3] = gen_reg_rtx (CCFPmode);
+})
+
+(define_insn "*vsx_tdiv<mode>3_internal"
+ [(set (match_operand:CCFP 0 "cc_reg_operand" "=x,x")
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")
+ (match_operand:VSX_B 2 "vsx_register_operand" "<VSr>,wa")]
+ UNSPEC_VSX_TDIV))]
+ "VECTOR_UNIT_VSX_P (<MODE>mode)"
+ "x<VSv>tdiv<VSs> %0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
@@ -473,12 +501,38 @@ (define_insn "vsx_rsqrte<mode>2"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
-(define_insn "vsx_tsqrt<mode>2"
- [(set (match_operand:VSX_B 0 "vsx_register_operand" "=<VSr>,?wa")
- (unspec:VSX_B [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]
- UNSPEC_VSX_TSQRT))]
+;; *tsqrt* returning the fg flag
+(define_expand "vsx_tsqrt<mode>2_fg"
+ [(set (match_dup 3)
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")]
+ UNSPEC_VSX_TSQRT))
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (gt:SI (match_dup 3)
+ (const_int 0)))]
+ "VECTOR_UNIT_VSX_P (<MODE>mode)"
+{
+ operands[3] = gen_reg_rtx (CCFPmode);
+})
+
+;; *tsqrt* returning the fe flag
+(define_expand "vsx_tsqrt<mode>2_fe"
+ [(set (match_dup 3)
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")]
+ UNSPEC_VSX_TSQRT))
+ (set (match_operand:SI 0 "gpc_reg_operand" "")
+ (eq:SI (match_dup 3)
+ (const_int 0)))]
+ "VECTOR_UNIT_VSX_P (<MODE>mode)"
+{
+ operands[3] = gen_reg_rtx (CCFPmode);
+})
+
+(define_insn "*vsx_tsqrt<mode>2_internal"
+ [(set (match_operand:CCFP 0 "cc_reg_operand" "=x,x")
+ (unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "<VSr>,wa")]
+ UNSPEC_VSX_TSQRT))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
- "x<VSv>tsqrt<VSs> %x0,%x1"
+ "x<VSv>tsqrt<VSs> %0,%x1"
[(set_attr "type" "<VStype_simple>")
(set_attr "fp_type" "<VSfptype_simple>")])
Index: gcc/config/rs6000/rs6000.h
===================================================================
--- gcc/config/rs6000/rs6000.h (revision 148504)
+++ gcc/config/rs6000/rs6000.h (working copy)
@@ -3224,8 +3224,10 @@ enum rs6000_builtins
VSX_BUILTIN_XSRSQRTEDP,
VSX_BUILTIN_XSSQRTDP,
VSX_BUILTIN_XSSUBDP,
- VSX_BUILTIN_XSTDIVDP,
- VSX_BUILTIN_XSTSQRTDP,
+ VSX_BUILTIN_XSTDIVDP_FE,
+ VSX_BUILTIN_XSTDIVDP_FG,
+ VSX_BUILTIN_XSTSQRTDP_FE,
+ VSX_BUILTIN_XSTSQRTDP_FG,
VSX_BUILTIN_XVABSDP,
VSX_BUILTIN_XVABSSP,
VSX_BUILTIN_XVADDDP,
@@ -3302,10 +3304,14 @@ enum rs6000_builtins
VSX_BUILTIN_XVSQRTSP,
VSX_BUILTIN_XVSUBDP,
VSX_BUILTIN_XVSUBSP,
- VSX_BUILTIN_XVTDIVDP,
- VSX_BUILTIN_XVTDIVSP,
- VSX_BUILTIN_XVTSQRTDP,
- VSX_BUILTIN_XVTSQRTSP,
+ VSX_BUILTIN_XVTDIVDP_FE,
+ VSX_BUILTIN_XVTDIVDP_FG,
+ VSX_BUILTIN_XVTDIVSP_FE,
+ VSX_BUILTIN_XVTDIVSP_FG,
+ VSX_BUILTIN_XVTSQRTDP_FE,
+ VSX_BUILTIN_XVTSQRTDP_FG,
+ VSX_BUILTIN_XVTSQRTSP_FE,
+ VSX_BUILTIN_XVTSQRTSP_FG,
VSX_BUILTIN_XXSEL_2DI,
VSX_BUILTIN_XXSEL_2DF,
VSX_BUILTIN_XXSEL_4SI,
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 148504)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -2294,7 +2294,7 @@ (define_expand "bswaphi2"
""
{
if (!REG_P (operands[0]) && !REG_P (operands[1]))
- operands[1] = force_reg (SImode, operands[1]);
+ operands[1] = force_reg (HImode, operands[1]);
})
(define_insn "bswaphi2_internal"
Index: gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c (revision 148504)
+++ gcc/testsuite/gcc.target/powerpc/vsx-builtin-2.c (working copy)
@@ -17,8 +17,6 @@
/* { dg-final { scan-assembler "xvnabssp" } } */
/* { dg-final { scan-assembler "xvresp" } } */
/* { dg-final { scan-assembler "xvrsqrtesp" } } */
-/* { dg-final { scan-assembler "xvtsqrtsp" } } */
-/* { dg-final { scan-assembler "xvtdivsp" } } */
void use_builtins (__vector float *p, __vector float *q, __vector float *r, __vector float *s)
{
@@ -37,6 +35,4 @@ void use_builtins (__vector float *p, __
p[12] = __builtin_vsx_xvnmsubsp (q[12], r[12], s[12]);
p[13] = __builtin_vsx_xvresp (q[13]);
p[14] = __builtin_vsx_xvrsqrtesp (q[14]);
- p[15] = __builtin_vsx_xvtsqrtsp (q[15]);
- p[16] = __builtin_vsx_xvtdivsp (q[16], r[16]);
}
Index: gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c (revision 0)
+++ gcc/testsuite/gcc.target/powerpc/vsx-builtin-6.c (revision 0)
@@ -0,0 +1,146 @@
+/* { dg-do compile { target { powerpc*-*-* } } } */
+/* { dg-skip-if "" { powerpc*-*-darwin* } { "*" } { "" } } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mcpu=power7" } */
+
+/* Check whether tdiv and tsqrt instructions generate the correct code. */
+/* Each of the *tdiv* and *tsqrt* instructions should be generated exactly 3
+ times (the two calls in the _1 function should be combined). */
+/* { dg-final { scan-assembler-times "xstdivdp" 3 } } */
+/* { dg-final { scan-assembler-times "xvtdivdp" 3 } } */
+/* { dg-final { scan-assembler-times "xvtdivsp" 3 } } */
+/* { dg-final { scan-assembler-times "xstsqrtdp" 3 } } */
+/* { dg-final { scan-assembler-times "xvtsqrtdp" 3 } } */
+/* { dg-final { scan-assembler-times "xvtsqrtsp" 3 } } */
+
+void test_div_df_1 (double a, double b, int *p)
+{
+ p[0] = __builtin_vsx_xstdivdp_fe (a, b);
+ p[1] = __builtin_vsx_xstdivdp_fg (a, b);
+}
+
+int *test_div_df_2 (double a, double b, int *p)
+{
+ if (__builtin_vsx_xstdivdp_fe (a, b))
+ *p++ = 1;
+
+ return p;
+}
+
+int *test_div_df_3 (double a, double b, int *p)
+{
+ if (__builtin_vsx_xstdivdp_fg (a, b))
+ *p++ = 1;
+
+ return p;
+}
+
+void test_sqrt_df_1 (double a, int *p)
+{
+ p[0] = __builtin_vsx_xstsqrtdp_fe (a);
+ p[1] = __builtin_vsx_xstsqrtdp_fg (a);
+}
+
+int *test_sqrt_df_2 (double a, int *p)
+{
+ if (__builtin_vsx_xstsqrtdp_fe (a))
+ *p++ = 1;
+
+ return p;
+}
+
+int *test_sqrt_df_3 (double a, int *p)
+{
+ if (__builtin_vsx_xstsqrtdp_fg (a))
+ *p++ = 1;
+
+ return p;
+}
+
+void test_div_v2df_1 (__vector double *a, __vector double *b, int *p)
+{
+ p[0] = __builtin_vsx_xvtdivdp_fe (*a, *b);
+ p[1] = __builtin_vsx_xvtdivdp_fg (*a, *b);
+}
+
+int *test_div_v2df_2 (__vector double *a, __vector double *b, int *p)
+{
+ if (__builtin_vsx_xvtdivdp_fe (*a, *b))
+ *p++ = 1;
+
+ return p;
+}
+
+int *test_div_v2df_3 (__vector double *a, __vector double *b, int *p)
+{
+ if (__builtin_vsx_xvtdivdp_fg (*a, *b))
+ *p++ = 1;
+
+ return p;
+}
+
+void test_sqrt_v2df_1 (__vector double *a, int *p)
+{
+ p[0] = __builtin_vsx_xvtsqrtdp_fe (*a);
+ p[1] = __builtin_vsx_xvtsqrtdp_fg (*a);
+}
+
+int *test_sqrt_v2df_2 (__vector double *a, int *p)
+{
+ if (__builtin_vsx_xvtsqrtdp_fe (*a))
+ *p++ = 1;
+
+ return p;
+}
+
+int *test_sqrt_v2df_3 (__vector double *a, int *p)
+{
+ if (__builtin_vsx_xvtsqrtdp_fg (*a))
+ *p++ = 1;
+
+ return p;
+}
+
+void test_div_v4sf_1 (__vector float *a, __vector float *b, int *p)
+{
+ p[0] = __builtin_vsx_xvtdivsp_fe (*a, *b);
+ p[1] = __builtin_vsx_xvtdivsp_fg (*a, *b);
+}
+
+int *test_div_v4sf_2 (__vector float *a, __vector float *b, int *p)
+{
+ if (__builtin_vsx_xvtdivsp_fe (*a, *b))
+ *p++ = 1;
+
+ return p;
+}
+
+int *test_div_v4sf_3 (__vector float *a, __vector float *b, int *p)
+{
+ if (__builtin_vsx_xvtdivsp_fg (*a, *b))
+ *p++ = 1;
+
+ return p;
+}
+
+void test_sqrt_v4sf_1 (__vector float *a, int *p)
+{
+ p[0] = __builtin_vsx_xvtsqrtsp_fe (*a);
+ p[1] = __builtin_vsx_xvtsqrtsp_fg (*a);
+}
+
+int *test_sqrt_v4sf_2 (__vector float *a, int *p)
+{
+ if (__builtin_vsx_xvtsqrtsp_fe (*a))
+ *p++ = 1;
+
+ return p;
+}
+
+int *test_sqrt_v4sf_3 (__vector float *a, int *p)
+{
+ if (__builtin_vsx_xvtsqrtsp_fg (*a))
+ *p++ = 1;
+
+ return p;
+}
Index: gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c (revision 148504)
+++ gcc/testsuite/gcc.target/powerpc/vsx-builtin-1.c (working copy)
@@ -14,11 +14,9 @@
/* { dg-final { scan-assembler "xvmindp" } } */
/* { dg-final { scan-assembler "xvsqrtdp" } } */
/* { dg-final { scan-assembler "xvrsqrtedp" } } */
-/* { dg-final { scan-assembler "xvtsqrtdp" } } */
/* { dg-final { scan-assembler "xvabsdp" } } */
/* { dg-final { scan-assembler "xvnabsdp" } } */
/* { dg-final { scan-assembler "xvredp" } } */
-/* { dg-final { scan-assembler "xvtdivdp" } } */
void use_builtins (__vector double *p, __vector double *q, __vector double *r, __vector double *s)
{
@@ -37,6 +35,4 @@ void use_builtins (__vector double *p, _
p[12] = __builtin_vsx_xvnmsubdp (q[12], r[12], s[12]);
p[13] = __builtin_vsx_xvredp (q[13]);
p[14] = __builtin_vsx_xvrsqrtedp (q[14]);
- p[15] = __builtin_vsx_xvtsqrtdp (q[15]);
- p[16] = __builtin_vsx_xvtdivdp (q[16], r[16]);
}
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meissner@linux.vnet.ibm.com