This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
[power7-meissner] Add VSX xxsldwi support; Add debug switches -mno-allow-df-permute and -mno-allow-movmisalign
- From: Michael Meissner <meissner at linux dot vnet dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 3 Jun 2009 12:48:06 -0400
- Subject: [power7-meissner] Add VSX xxsldwi support; Add debug switches -mno-allow-df-permute and -mno-allow-movmisalign
I added support for the VSX version of vector shift (xxsldwi) that shifts by
words instead of octects, but it can shift any VSX (traditional floating point
or Altivec) register.
I also added two debug switches. -mno-allow-movmisalign disables the
movmisalign support for V2DF/V2DI. -mno-allow-df-permute disables using the
vperm instruction on V2DF/V2DI.
2009-06-03 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/vector.md (movmisalign<mode>): Add support for
debug -mno-allow-misalign switch.
(vec_shl_<mode>): Add support for VSX xxsldwi.
(vec_shr_<mode>): Ditto.
* config/rs6000/rs6000.opt (-mallow-movmisalign): New debug
switch.
(-mallow-df-permute): Ditto.
* config/rs6000/rs6000.c (rs6000_builtin_vec_perm): Add support
for -mno-allow-df-permute debug switch.
Index: gcc/config/rs6000/vector.md
===================================================================
--- gcc/config/rs6000/vector.md (revision 148135)
+++ gcc/config/rs6000/vector.md (working copy)
@@ -793,7 +793,7 @@ (define_expand "vec_realign_load_<mode>"
(define_expand "movmisalign<mode>"
[(set (match_operand:VEC_N 0 "vfloat_operand" "")
(match_operand:VEC_N 1 "vfloat_operand" ""))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
+ "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN"
"")
@@ -802,7 +802,6 @@ (define_expand "movmisalign<mode>"
;; General shift amounts can be supported using vslo + vsl. We're
;; not expecting to see these yet (the vectorizer currently
;; generates only shifts divisible by byte_size).
-;; TODO, add VSX xxsldwi support for word oriented shifts
(define_expand "vec_shl_<mode>"
[(match_operand:VEC_L 0 "vlogical_operand" "")
(match_operand:VEC_L 1 "vlogical_operand" "")
@@ -811,7 +810,8 @@ (define_expand "vec_shl_<mode>"
"
{
rtx bitshift = operands[2];
- rtx byteshift = gen_reg_rtx (QImode);
+ rtx shift;
+ rtx insn;
HOST_WIDE_INT bitshift_val;
HOST_WIDE_INT byteshift_val;
@@ -821,9 +821,20 @@ (define_expand "vec_shl_<mode>"
if (bitshift_val & 0x7)
FAIL;
byteshift_val = bitshift_val >> 3;
- byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
- emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
- byteshift));
+ if (TARGET_VSX && (byteshift_val & 0x3) == 0)
+ {
+ shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
+ insn = gen_vsx_xxsldwi_<mode> (operands[0], operands[1], operands[1],
+ shift);
+ }
+ else
+ {
+ shift = gen_rtx_CONST_INT (QImode, byteshift_val);
+ insn = gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
+ shift);
+ }
+
+ emit_insn (insn);
DONE;
}")
@@ -832,7 +843,6 @@ (define_expand "vec_shl_<mode>"
;; General shift amounts can be supported using vsro + vsr. We're
;; not expecting to see these yet (the vectorizer currently
;; generates only shifts divisible by byte_size).
-;; TODO, add VSX xxsldwi support for word oriented shifts
(define_expand "vec_shr_<mode>"
[(match_operand:VEC_L 0 "vlogical_operand" "")
(match_operand:VEC_L 1 "vlogical_operand" "")
@@ -841,7 +851,8 @@ (define_expand "vec_shr_<mode>"
"
{
rtx bitshift = operands[2];
- rtx byteshift = gen_reg_rtx (QImode);
+ rtx shift;
+ rtx insn;
HOST_WIDE_INT bitshift_val;
HOST_WIDE_INT byteshift_val;
@@ -851,9 +862,20 @@ (define_expand "vec_shr_<mode>"
if (bitshift_val & 0x7)
FAIL;
byteshift_val = 16 - (bitshift_val >> 3);
- byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
- emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
- byteshift));
+ if (TARGET_VSX && (byteshift_val & 0x3) == 0)
+ {
+ shift = gen_rtx_CONST_INT (QImode, byteshift_val >> 2);
+ insn = gen_vsx_xxsldwi_<mode> (operands[0], operands[1], operands[1],
+ shift);
+ }
+ else
+ {
+ shift = gen_rtx_CONST_INT (QImode, byteshift_val);
+ insn = gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
+ shift);
+ }
+
+ emit_insn (insn);
DONE;
}")
Index: gcc/config/rs6000/rs6000.opt
===================================================================
--- gcc/config/rs6000/rs6000.opt (revision 148135)
+++ gcc/config/rs6000/rs6000.opt (working copy)
@@ -139,6 +139,14 @@ mdisallow-float-in-lr-ctr
Target Undocumented Var(TARGET_DISALLOW_FLOAT_IN_LR_CTR) Init(-1)
; Disallow floating point in LR or CTR, causes some reload bugs
+mallow-movmisalign
+Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1)
+; Allow/disallow the movmisalign in DF/DI vectors
+
+mallow-df-permute
+Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) Init(-1)
+; Allow/disallow permutation of DF/DI vectors
+
mupdate
Target Report Var(TARGET_UPDATE) Init(1)
Generate load/store with update instructions
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 148135)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -2851,10 +2851,16 @@ rs6000_builtin_vec_perm (tree type, tree
break;
case V2DFmode:
+ if (!TARGET_ALLOW_DF_PERMUTE)
+ return NULL_TREE;
+
d = rs6000_builtin_decls[ALTIVEC_BUILTIN_VPERM_2DF];
break;
case V2DImode:
+ if (!TARGET_ALLOW_DF_PERMUTE)
+ return NULL_TREE;
+
d = (uns_p
? rs6000_builtin_decls[ALTIVEC_BUILTIN_VPERM_2DI_UNS]
: rs6000_builtin_decls[ALTIVEC_BUILTIN_VPERM_2DI]);
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meissner@linux.vnet.ibm.com