Index: ChangeLog.spu-4_5 =================================================================== --- ChangeLog.spu-4_5 (revision 147229) +++ ChangeLog.spu-4_5 (working copy) @@ -1,3 +1,31 @@ +2009-05-18 Ulrich Weigand + Revital Eres + + * varasm.c (text_part_section): Pass current_function_decl to + get_named_section. + (current_function_section): Likewise. + (assemble_start_function): Set in_part_section_p. + * bb-reorder.c (fix_up_fall_thru_edges): Check for any_condjump_p. + * config/spu/spu.c (spu_override_options): Change stub size. + (spu_expand_prologue): Add REG_BRANCH_INFO to mark prologue. + (spu_expand_epilogue): Add REG_BRANCH_INFO to mark epilogue. + (begin_critical_section): Change Recognition of prologue, + epilogue and icache sequence. + (is_ibranch_seq_end): Change check. + (end_critical_section): Change Recognition of prologue, epilogue + and icache sequence. + (record_jump_table): Use last_basic_block. + (spu_start_new_section): Re-set + estimate_number_of_external_branches_in_section. + (record_link_elements_liveness): Remove. + (record_branch_info): Add condition. + (final_prescan_insn): Change analysis for branch info. + (spu_machine_dependent_reorg): Remove calls to + record_link_elements_liveness. + (spu_function_ok_for_sibcall): Remove TARGET_SOFTWARE_ICACHE check. + * config/spu/spu-elf.h: Define msoftware-icache linker options. + * config/spu/spu.md: Change icache sequance. + 2009-01-25 Revital Eres * bb-reorder.c (create_sections): Fix comment. Index: testsuite/gcc.target/spu/icache-1.c =================================================================== --- testsuite/gcc.target/spu/icache-1.c (revision 147229) +++ testsuite/gcc.target/spu/icache-1.c (working copy) @@ -51,6 +51,6 @@ main (void) return 0; } -/* { dg-final { scan-rtl-dump-times "icache_bi_handler" 1 "fpart" } } */ +/* { dg-final { scan-rtl-dump-times "icache_ptr_handler" 1 "fpart" } } */ /* { dg-final { cleanup-rtl-dump "fpart" } } */ Index: testsuite/gcc.target/spu/icache-2.c =================================================================== --- testsuite/gcc.target/spu/icache-2.c (revision 147229) +++ testsuite/gcc.target/spu/icache-2.c (working copy) @@ -23,6 +23,6 @@ int main() } } -/* { dg-final { scan-rtl-dump-times "icache_bi_handler" 1 "fpart" } } */ +/* { dg-final { scan-rtl-dump-times "icache_ptr_handler" 1 "fpart" } } */ /* { dg-final { cleanup-rtl-dump "fpart" } } */ Index: testsuite/ChangeLog.spu-4_5 =================================================================== --- testsuite/ChangeLog.spu-4_5 (revision 147229) +++ testsuite/ChangeLog.spu-4_5 (working copy) @@ -1,3 +1,8 @@ +2009-05-18 Revital Eres + + * gcc.target/spu/icache-1.c: Change dump file check. + * gcc.target/spu/icache-2.c: Likewise. + 2009-01-25 Revital Eres * gcc.target/spu/icache-3.c: New testcase. Index: varasm.c =================================================================== --- varasm.c (revision 147229) +++ varasm.c (working copy) @@ -771,7 +771,8 @@ text_part_section (int section_id) section_name = ACONCAT ((prefix_str, section_id_str, NULL)); last_part_text_section_name = ggc_strdup (section_name); - return get_named_section (NULL, last_part_text_section_name, 0); + return get_named_section (current_function_decl, + last_part_text_section_name, 0); } @@ -947,7 +948,8 @@ current_function_section (void) DECL_ALIGN (current_function_decl)); #else if (in_part_section_p) - return get_named_section (NULL, last_part_text_section_name, 0); + return get_named_section (current_function_decl, + last_part_text_section_name, 0); return (in_cold_section_p ? unlikely_text_section () : hot_function_section (current_function_decl)); @@ -1869,6 +1871,7 @@ assemble_start_function (tree decl, cons } in_cold_section_p = first_function_block_is_cold; + in_part_section_p = false; /* Switch to the correct text section for the start of the function. */ Index: bb-reorder.c =================================================================== --- bb-reorder.c (revision 147229) +++ bb-reorder.c (working copy) @@ -1911,8 +1911,10 @@ fix_up_fall_thru_edges (void) old_jump = BB_END (cur_bb); /* Find the jump instruction, if there is one. */ - - if (cond_jump) + /* For exceptions there are two out-edges (the fall-through + after the call, and the exception edge), but no + conditional jump. */ + if (cond_jump && any_condjump_p (old_jump)) { if (!(cond_jump->flags & EDGE_CROSSING)) cond_jump_crosses = false; Index: config/spu/spu.c =================================================================== --- config/spu/spu.c (revision 147229) +++ config/spu/spu.c (working copy) @@ -465,7 +465,7 @@ spu_override_options (void) flag_partition_functions_into_sections = ICACHE_LINESIZE; flag_function_sections = 1; /* A stub is 8 words of information. */ - spu_stub_size = 32; + spu_stub_size = 16; fix_range ("75-79"); } @@ -2124,6 +2124,14 @@ spu_expand_prologue (void) } } + if (TARGET_SOFTWARE_ICACHE) + { + insn = emit_insn (gen_blockage ()); + add_reg_note (insn, REG_BRANCH_INFO, + gen_rtx_SYMBOL_REF (VOIDmode, + ggc_strdup ("prologue_end"))); + } + emit_note (NOTE_INSN_DELETED); } @@ -2156,6 +2164,15 @@ spu_expand_epilogue (bool sibcall_p) || (current_function_is_leaf && TARGET_SOFTWARE_ICACHE)) total_size += STACK_POINTER_OFFSET; + if (TARGET_SOFTWARE_ICACHE) + { + rtx insn = emit_insn (gen_blockage ()); + + add_reg_note (insn, REG_BRANCH_INFO, + gen_rtx_SYMBOL_REF (VOIDmode, + ggc_strdup ("epilogue_start"))); + } + if (total_size > 0) { if (cfun->calls_alloca) @@ -2517,48 +2534,37 @@ begin_critical_section (rtx insn, enum c if (!INSN_P (insn)) return false; - if (GET_CODE (PATTERN (insn)) == PARALLEL) - return false; - - set = single_set (insn); - - if (set != 0) + if (TARGET_SOFTWARE_ICACHE) { - rtx src, dest; - - src = SET_SRC (set); - dest = SET_DEST (set); - - if (TARGET_SOFTWARE_ICACHE - && REG_P (dest) - && (REGNO (dest) == STACK_POINTER_REGNUM) - && (GET_CODE (src)) == PLUS) + rtx note = find_reg_note (insn, REG_BRANCH_INFO, NULL_RTX); + if (note) { - rtx op1, op2; - - op1 = XEXP (src, 0); - op2 = XEXP (src, 1); - if (REG_P (op1) - && (REGNO (op1) == STACK_POINTER_REGNUM) - && (GET_CODE (op2) == CONST_INT) - && (INTVAL (op2) > 0)) + const char *info = XSTR (XEXP (note, 0), 0); + + if (strcmp (info, "epilogue_start") == 0) { *type = EPILOGUE; - dump_critical_section_info (EPILOGUE, true, insn); + dump_critical_section_info (EPILOGUE, true, insn); + return true; + } + if (strcmp (info, "ibranch_seq") == 0) + { + *type = IBRANCH_SEQ; + dump_critical_section_info (IBRANCH_SEQ, true, insn); return true; } } - /* The interval from lqr $76, func_ptr to the - branch indirect is a critical section. */ - if (TARGET_SOFTWARE_ICACHE - && REG_P (dest) - && (REGNO (dest) == 76) - && (REG_P (src))) - { - *type = IBRANCH_SEQ; - dump_critical_section_info (IBRANCH_SEQ, true, insn); - return true; - } + } + + set = single_set (insn); + + if (set != 0) + { + rtx src, dest; + + src = SET_SRC (set); + dest = SET_DEST (set); + /* We are looking for this type of instruction: (insn (set (reg) @@ -2635,6 +2641,9 @@ is_ibranch_seq_end (rtx insn) if (GET_CODE (SET_DEST (set)) != PC) abort (); + if (REG_P (src) && REGNO (src) == 75) + return true; + if (GET_CODE (src) == IF_THEN_ELSE) { rtx lab = 0; @@ -2670,58 +2679,44 @@ is_ibranch_seq_end (rtx insn) static bool end_critical_section (rtx insn, enum critical_section_type *type) { - rtx body, set; + rtx body; if (!INSN_P (insn)) return false; - body = PATTERN (insn); - - if (TARGET_SOFTWARE_ICACHE - && (JUMP_P (insn) || CALL_P (insn)) - && is_ibranch_seq_end (insn)) - { - *type = IBRANCH_SEQ; - dump_critical_section_info (IBRANCH_SEQ, false, insn); - return true; - } - if (TARGET_SOFTWARE_ICACHE - && JUMP_P (insn) - && GET_CODE (PATTERN (insn)) == RETURN) - { - *type = EPILOGUE; - dump_critical_section_info (EPILOGUE, false, insn); - return true; - } - - set = single_set (insn); - - if (TARGET_SOFTWARE_ICACHE && set) + if (TARGET_SOFTWARE_ICACHE) { - rtx src = SET_SRC (set); - rtx dest = SET_DEST (set); - - if (TARGET_SOFTWARE_ICACHE - && REG_P (dest) - && (REGNO (dest) == STACK_POINTER_REGNUM) - && (GET_CODE (src)) == PLUS) + rtx note = find_reg_note (insn, REG_BRANCH_INFO, NULL_RTX); + if (note) { - rtx op1, op2; - - op1 = XEXP (src, 0); - op2 = XEXP (src, 1); - if (REG_P (op1) - && (REGNO (op1) == STACK_POINTER_REGNUM) - && (GET_CODE (op2) == CONST_INT) - && (INTVAL (op2) < 0)) + const char *info = XSTR (XEXP (note, 0), 0); + + if (strcmp (info, "prologue_end") == 0) { *type = PROLOGUE; - dump_critical_section_info (PROLOGUE, false, insn); + dump_critical_section_info (PROLOGUE, false, insn); return true; } } + + if ((JUMP_P (insn) || CALL_P (insn)) && is_ibranch_seq_end (insn)) + { + *type = IBRANCH_SEQ; + dump_critical_section_info (IBRANCH_SEQ, false, insn); + return true; + } + + if ((JUMP_P (insn) && GET_CODE (PATTERN (insn)) == RETURN) + || (CALL_P (insn) && SIBLING_CALL_P (insn))) + { + *type = EPILOGUE; + dump_critical_section_info (EPILOGUE, false, insn); + return true; + } } - + + body = PATTERN (insn); + /* We are looking for the following type of instruction: (insn (parallel [ @@ -2833,8 +2828,8 @@ record_jump_table (rtx ila_insn) bool found_jump_table = false; unsigned HOST_WIDE_INT size = 0; - bb_aux = (bool *)xmalloc (n_basic_blocks * sizeof (bool)); - memset (bb_aux, false, n_basic_blocks * sizeof (bool)); + bb_aux = (bool *)xmalloc (last_basic_block * sizeof (bool)); + memset (bb_aux, false, last_basic_block * sizeof (bool)); set = single_set (ila_insn); @@ -2872,7 +2867,7 @@ record_jump_table (rtx ila_insn) /* Mark the bb's between the jump-table and the code that reads the table so they reside in the same section. */ - for (i = 0; i < n_basic_blocks; i++) + for (i = 0; i < last_basic_block; i++) if (bb_aux[i] == true) BASIC_BLOCK (i)->il.rtl->skip = 1; } @@ -2945,6 +2940,8 @@ spu_start_new_section (int bb_index, uns /* Estimate the number of external branch limit in the current section. */ if (TARGET_SOFTWARE_ICACHE) { + if (last_section_size == 0) + estimate_number_of_external_branches_in_section = 0; if (bb->flags & BB_FIRST_AFTER_SECTION_SWITCH) estimate_number_of_external_branches_in_section = 0; else if (!(single_succ_p (bb) && single_succ_edge (bb)->dest == bb)) @@ -3065,72 +3062,6 @@ spu_dont_create_jumptable (unsigned int return false; } -/* All inter-block branches can cause cache misses, and therefore - evictions. During eviction, a block is deallocated from the cache. - A stack back-trace is performed to locate the first return pointer to - the evicted block. This back-trace process requires knowlege about - the current state of liveness of the first three link elements. - Therefor, all external branches must be labeled with a 3 bit link - liveness indicator. - - liveness - indicator meaning - --------- ------------------------------------- - 1.. indicates the lr itself is live - .1. indicates the value *(sp+16) is live - ..1 indicates the value *(*sp+16) is live - - For example, on entry to a function the liveness indicator would be - "101" because the link register is live, but the link value in the - current stack frame is not while the the link value in the previous - stack frame is valid. After, the link register is saved in a non-leaf - function, the indicator would be "011". If the function then allocates - a new stack frame, the indicator would be "001". If a leaf proceedure - creates a new stack frame, the indicator would transition from "101" - to "100". - TODO: If we always save lr and do not break the sequence between - stack-setup and tear-down parts we have the following two scenarios: - 1. inter-functions calls (including sibling calls) -- 101 - 2. intra-function jumps between stack-setup part and tear-down part -- - 001. - The linker can deduce the states (GCC does not have to pass the - lr information. To create smaller critical sections GCC should - calculate the states and pass them to the linker. */ -static void -record_link_elements_liveness (void) -{ - rtx insn; - - gcc_assert (TARGET_SOFTWARE_ICACHE); - for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) - { - rtx set; - - if (!INSN_P (insn)) - continue; - - /* Fix lqa r75,__icache_ptr_handler$lr_live. */ - set = single_set (insn); - if (set - && REG_P (SET_DEST (set)) - && (REGNO (SET_DEST (set)) == 75) - && MEM_P (SET_SRC (set)) - && GET_CODE (XEXP (XEXP (SET_SRC (set), 0), 0)) == SYMBOL_REF) - { - rtx symbol_ref; - char *new_symbol; - const char *str; - - symbol_ref = XEXP (XEXP (SET_SRC (set), 0), 0); - str = XSTR (symbol_ref, 0); - new_symbol = (char *) alloca (2 + 2 * HOST_BITS_PER_INT / 4 + 1); - sprintf (new_symbol, str); - strcat (new_symbol, "5"); - XSTR (symbol_ref, 0) = ggc_strdup (new_symbol); - } - } -} - /* A structure to hold information for each branch instruction. For the software i-cache scheme we emit sequences of code that are later been construction by the linker into cache lines. To help the @@ -3208,6 +3139,9 @@ record_branch_info (void) src = SET_SRC (set); if (GET_CODE (SET_DEST (set)) != PC) abort (); + + if (REG_P (src)) + continue; if (GET_CODE (src) == IF_THEN_ELSE) { @@ -3425,15 +3359,23 @@ print_operand_punct_valid_p (int c) void final_prescan_insn (rtx insn, - rtx *opvec ATTRIBUTE_UNUSED, - int noperands ATTRIBUTE_UNUSED) + rtx *opvec ATTRIBUTE_UNUSED, + int noperands ATTRIBUTE_UNUSED) { - rtx branch_info = find_reg_note (insn, REG_BRANCH_INFO, NULL_RTX); + rtx branch_info; - if (branch_info == NULL_RTX) - global_branch_info = NULL; - else - global_branch_info = XSTR (XEXP (branch_info, 0), 0); + global_branch_info = NULL; + + if (!TARGET_SOFTWARE_ICACHE || !INSN_P (insn)) + return; + + if (GET_CODE (insn) == JUMP_INSN + || GET_CODE (insn) == CALL_INSN) + { + branch_info = find_reg_note (insn, REG_BRANCH_INFO, NULL_RTX); + if (branch_info != NULL) + global_branch_info = XSTR (XEXP (branch_info, 0), 0); + } } @@ -3853,7 +3795,6 @@ spu_machine_dependent_reorg (void) if (TARGET_SOFTWARE_ICACHE) { record_branch_info (); - record_link_elements_liveness (); } return; @@ -4054,7 +3995,6 @@ spu_machine_dependent_reorg (void) if (TARGET_SOFTWARE_ICACHE) { record_branch_info (); - record_link_elements_liveness (); } free_bb_for_insn (); @@ -6564,7 +6504,7 @@ spu_unwind_word_mode (void) static bool spu_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) { - return decl && !TARGET_LARGE_MEM && !TARGET_SOFTWARE_ICACHE; + return decl && !TARGET_LARGE_MEM; } /* We need to correctly update the back chain pointer and the Available Index: config/spu/spu-elf.h =================================================================== --- config/spu/spu-elf.h (revision 147229) +++ config/spu/spu-elf.h (working copy) @@ -77,7 +77,8 @@ %{mno-atomic-updates:-lgcc_cachemgr_nonatomic; :-lgcc_cachemgr} \ %k libraries because lgcc_cache* did not seem to work -- perhaps a bug in the specs Index: config/spu/spu.md =================================================================== --- config/spu/spu.md (revision 147229) +++ config/spu/spu.md (working copy) @@ -2693,9 +2693,9 @@ { if (TARGET_SOFTWARE_ICACHE && (REGNO (operands[0]) != LINK_REGISTER_REGNUM)) { - rtx tag_size_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_size"); - rtx tag_arr_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array"); - rtx icache_handler_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_ptr___icache_bi_handler"); + rtx tag_size_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_mask"); + rtx tag_arr_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_pointer"); + rtx icache_handler_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_ptr_handler1"); rtx linesize_sym = gen_rtx_SYMBOL_REF (SImode, "__icache_neg_log2_linesize"); rtx r75 = gen_rtx_REG (SImode, 75); rtx r75_ = gen_rtx_REG (TImode, 75); @@ -2706,9 +2706,10 @@ rtx r78_ = gen_rtx_REG (TImode, 78); rtx r79 = gen_rtx_REG (SImode, 79); rtx r79_ = gen_rtx_REG (TImode, 79); + rtx insn; /* Load function pointer. */ - emit_insn (gen_iorsi3 (r76, operands[0], GEN_INT(0))); + emit_move_insn (r76, operands[0]); /* Load instruction cache miss handler descriptor. */ emit_insn (gen_spu_lqa (r75_, icache_handler_sym)); @@ -2720,7 +2721,10 @@ /* Load cache tag for line associated with target IA. */ emit_insn (gen_rotm_si (r79, r76, plus_constant (linesize_sym, 4))); emit_insn (gen_andsi3 (r79, r79, r77)); - emit_insn (gen_spu_lqx (r79_, r78, r79)); + insn = emit_insn (gen_spu_lqx (r79_, r78, r79)); + add_reg_note (insn, REG_BRANCH_INFO, + gen_rtx_SYMBOL_REF (VOIDmode, + ggc_strdup ("ibranch_seq"))); /* Compare cache tag with tag of target IA. */ emit_insn (gen_rotm_si (r77, r76, linesize_sym)); @@ -3884,6 +3888,9 @@ selb\t%0,%4,%0,%3" rtx sindex = gen_reg_rtx (SImode); rtx addr = gen_reg_rtx (Pmode); + if (TARGET_SOFTWARE_ICACHE) + emit_insn (gen_blockage ()); + emit_move_insn (table, gen_rtx_LABEL_REF (SImode, operands[3])); emit_insn (gen_subsi3(index, operands[0], force_reg(SImode, operands[1]))); @@ -3912,9 +3919,9 @@ selb\t%0,%4,%0,%3" { if (TARGET_SOFTWARE_ICACHE) { - rtx tag_size_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_size"); - rtx tag_arr_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array"); - rtx icache_handler_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_ptr___icache_bi_handler"); + rtx tag_size_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_mask"); + rtx tag_arr_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_pointer"); + rtx icache_handler_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_ptr_handler1"); rtx linesize_sym = gen_rtx_SYMBOL_REF (SImode, "__icache_neg_log2_linesize"); rtx r75 = gen_rtx_REG (SImode, 75); rtx r75_ = gen_rtx_REG (TImode, 75); @@ -3925,9 +3932,10 @@ selb\t%0,%4,%0,%3" rtx r78_ = gen_rtx_REG (TImode, 78); rtx r79 = gen_rtx_REG (SImode, 79); rtx r79_ = gen_rtx_REG (TImode, 79); + rtx insn; /* Load function pointer. */ - emit_insn (gen_iorsi3 (r76, operands[0], GEN_INT(0))); + emit_move_insn (r76, operands[0]); /* Load instruction cache miss handler descriptor. */ emit_insn (gen_spu_lqa (r75_, icache_handler_sym)); @@ -3939,7 +3947,10 @@ selb\t%0,%4,%0,%3" /* Load cache tag for line associated with target IA. */ emit_insn (gen_rotm_si (r79, r76, plus_constant (linesize_sym, 4))); emit_insn (gen_andsi3 (r79, r79, r77)); - emit_insn (gen_spu_lqx (r79_, r78, r79)); + insn = emit_insn (gen_spu_lqx (r79_, r78, r79)); + add_reg_note (insn, REG_BRANCH_INFO, + gen_rtx_SYMBOL_REF (VOIDmode, + ggc_strdup ("ibranch_seq"))); /* Compare cache tag with tag of target IA. */ emit_insn (gen_rotm_si (r77, r76, linesize_sym)); @@ -3976,9 +3987,9 @@ selb\t%0,%4,%0,%3" } else { - rtx tag_size_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_size"); - rtx tag_arr_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array"); - rtx icache_handler_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_ptr___icache_bi_handler"); + rtx tag_size_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_mask"); + rtx tag_arr_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_pointer"); + rtx icache_handler_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_ptr_handler5"); rtx linesize_sym = gen_rtx_SYMBOL_REF (SImode, "__icache_neg_log2_linesize"); rtx r75 = gen_rtx_REG (SImode, 75); rtx r75_ = gen_rtx_REG (TImode, 75); @@ -3989,9 +4000,10 @@ selb\t%0,%4,%0,%3" rtx r78_ = gen_rtx_REG (TImode, 78); rtx r79 = gen_rtx_REG (SImode, 79); rtx r79_ = gen_rtx_REG (TImode, 79); + rtx insn; /* Load function pointer. */ - emit_insn (gen_iorsi3 (r76, operands[0], GEN_INT(0))); + emit_move_insn (r76, XEXP (operands[0], 0)); /* Load instruction cache miss handler descriptor. */ emit_insn (gen_spu_lqa (r75_, icache_handler_sym)); @@ -4003,7 +4015,10 @@ selb\t%0,%4,%0,%3" /* Load cache tag for line associated with target IA. */ emit_insn (gen_rotm_si (r79, r76, plus_constant (linesize_sym, 4))); emit_insn (gen_andsi3 (r79, r79, r77)); - emit_insn (gen_spu_lqx (r79_, r78, r79)); + insn = emit_insn (gen_spu_lqx (r79_, r78, r79)); + add_reg_note (insn, REG_BRANCH_INFO, + gen_rtx_SYMBOL_REF (VOIDmode, + ggc_strdup ("ibranch_seq"))); /* Compare cache tag with tag of target IA. */ emit_insn (gen_rotm_si (r77, r76, linesize_sym)); @@ -4045,9 +4060,9 @@ selb\t%0,%4,%0,%3" } else { - rtx tag_size_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_size"); - rtx tag_arr_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array"); - rtx icache_handler_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_ptr___icache_bi_handler"); + rtx tag_size_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_mask"); + rtx tag_arr_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_pointer"); + rtx icache_handler_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_ptr_handler5"); rtx linesize_sym = gen_rtx_SYMBOL_REF (SImode, "__icache_neg_log2_linesize"); rtx r75 = gen_rtx_REG (SImode, 75); rtx r75_ = gen_rtx_REG (TImode, 75); @@ -4058,9 +4073,10 @@ selb\t%0,%4,%0,%3" rtx r78_ = gen_rtx_REG (TImode, 78); rtx r79 = gen_rtx_REG (SImode, 79); rtx r79_ = gen_rtx_REG (TImode, 79); + rtx insn; /* Load function pointer. */ - emit_insn (gen_iorsi3 (r76, operands[0], GEN_INT(0))); + emit_move_insn (r76, XEXP (operands[1], 0)); /* Load instruction cache miss handler descriptor. */ emit_insn (gen_spu_lqa (r75_, icache_handler_sym)); @@ -4072,7 +4088,10 @@ selb\t%0,%4,%0,%3" /* Load cache tag for line associated with target IA. */ emit_insn (gen_rotm_si (r79, r76, plus_constant (linesize_sym, 4))); emit_insn (gen_andsi3 (r79, r79, r77)); - emit_insn (gen_spu_lqx (r79_, r78, r79)); + insn = emit_insn (gen_spu_lqx (r79_, r78, r79)); + add_reg_note (insn, REG_BRANCH_INFO, + gen_rtx_SYMBOL_REF (VOIDmode, + ggc_strdup ("ibranch_seq"))); /* Compare cache tag with tag of target IA. */ emit_insn (gen_rotm_si (r77, r76, linesize_sym)); @@ -4117,9 +4136,9 @@ selb\t%0,%4,%0,%3" } else { - rtx tag_size_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_size"); - rtx tag_arr_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array"); - rtx icache_handler_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_ptr___icache_bi_handler"); + rtx tag_size_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_mask"); + rtx tag_arr_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_pointer"); + rtx icache_handler_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_ptr_handler5"); rtx linesize_sym = gen_rtx_SYMBOL_REF (SImode, "__icache_neg_log2_linesize"); rtx r75 = gen_rtx_REG (SImode, 75); rtx r75_ = gen_rtx_REG (TImode, 75); @@ -4130,9 +4149,10 @@ selb\t%0,%4,%0,%3" rtx r78_ = gen_rtx_REG (TImode, 78); rtx r79 = gen_rtx_REG (SImode, 79); rtx r79_ = gen_rtx_REG (TImode, 79); + rtx insn; /* Load function pointer. */ - emit_insn (gen_iorsi3 (r76, operands[0], GEN_INT(0))); + emit_move_insn (r76, XEXP (operands[0], 0)); /* Load instruction cache miss handler descriptor. */ emit_insn (gen_spu_lqa (r75_, icache_handler_sym)); @@ -4144,7 +4164,10 @@ selb\t%0,%4,%0,%3" /* Load cache tag for line associated with target IA. */ emit_insn (gen_rotm_si (r79, r76, plus_constant (linesize_sym, 4))); emit_insn (gen_andsi3 (r79, r79, r77)); - emit_insn (gen_spu_lqx (r79_, r78, r79)); + insn = emit_insn (gen_spu_lqx (r79_, r78, r79)); + add_reg_note (insn, REG_BRANCH_INFO, + gen_rtx_SYMBOL_REF (VOIDmode, + ggc_strdup ("ibranch_seq"))); /* Compare cache tag with tag of target IA. */ emit_insn (gen_rotm_si (r77, r76, linesize_sym)); @@ -4190,9 +4213,9 @@ selb\t%0,%4,%0,%3" } else { - rtx tag_size_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_size"); - rtx tag_arr_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array"); - rtx icache_handler_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_ptr___icache_bi_handler"); + rtx tag_size_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_mask"); + rtx tag_arr_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_tag_array_pointer"); + rtx icache_handler_sym = gen_rtx_SYMBOL_REF (Pmode, "__icache_ptr_handler5"); rtx linesize_sym = gen_rtx_SYMBOL_REF (SImode, "__icache_neg_log2_linesize"); rtx r75 = gen_rtx_REG (SImode, 75); rtx r75_ = gen_rtx_REG (TImode, 75); @@ -4203,9 +4226,10 @@ selb\t%0,%4,%0,%3" rtx r78_ = gen_rtx_REG (TImode, 78); rtx r79 = gen_rtx_REG (SImode, 79); rtx r79_ = gen_rtx_REG (TImode, 79); + rtx insn; /* Load function pointer. */ - emit_insn (gen_iorsi3 (r76, operands[0], GEN_INT(0))); + emit_move_insn (r76, XEXP (operands[1], 0)); /* Load instruction cache miss handler descriptor. */ emit_insn (gen_spu_lqa (r75_, icache_handler_sym)); @@ -4217,7 +4241,10 @@ selb\t%0,%4,%0,%3" /* Load cache tag for line associated with target IA. */ emit_insn (gen_rotm_si (r79, r76, plus_constant (linesize_sym, 4))); emit_insn (gen_andsi3 (r79, r79, r77)); - emit_insn (gen_spu_lqx (r79_, r78, r79)); + insn = emit_insn (gen_spu_lqx (r79_, r78, r79)); + add_reg_note (insn, REG_BRANCH_INFO, + gen_rtx_SYMBOL_REF (VOIDmode, + ggc_strdup ("ibranch_seq"))); /* Compare cache tag with tag of target IA. */ emit_insn (gen_rotm_si (r77, r76, linesize_sym));