This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[PATCH] Further i386/x86_64 length bugfixes


On Thu, May 21, 2009 at 03:15:32PM +0200, Uros Bizjak wrote:
> > Here is a small follow-up, when looking for the PLUS insns where both
> > 128 and -128 can use shortened immediate because add*/sub* can be chosen
> > for smaller length, I've missed cases which are inverting that test (== -128
> > instead of == 128).
> 
> This is also OK for mainline.

Here is a slightly larger followup.  This time I've been using
make check RUNTESTFLAGS="i386.exp --target_board=unix/\{-m32,-m64\}"
as source of -dp generated assembly for verification by my script posted
earlier.  That contains lots of weird i386 options and has much better
insn coverage than e.g. gcc cc1 files, even with -ftree-vectorize, because
e.g. all *intrin.h headers are sourced with various options and most
of the builtins actually used in code, etc.
This patch trims the number of errors reported by the script
from over 2300 to 53.  I've been using extensively AMD64 programming guide,
SSE5 programming guide and AVX programming guide, gas and binutils i386 opcode
tables to fix the various issues in gcc i386 attribute computations.
In addition to i386.exp make check also tested on the collection of cc1 files
from gcc I've been using already earlier.

Major changes in the patch include e.g. adding length_immediate 1 to
sse/mmx/avx instructions that have 1 byte immediate, using prefix_extra 1
for 3DNOW instructions which have 0f0f prefix, using prefix_extra 2
for SSE5 instructions which have 0f2[45] prefix and DREX byte or
prefix_extra 1 for SSE5 instructions with 0f7a prefix, not assuming
all prefix_0f instructions can be encoded in 2byte VEX prefix (prefix_0f
attribute is common to 0f, 0f0f, 0f38, 0f3a, 0f7a, ..., only 0f alone
can be encoded in 2byte VEX prefix, 0f38/0f3a can't).  Also the prefix_rep
and prefix_data16 defaults based on SF/DF mode resp. V2DF/TI aren't correct
for many instructions (various mov{,d,q}, sse5, etc.).  And (most of) mmx
unit instructions which have MODE_DI shouldn't have a REX prefix in 64-bit
mode.

Remaining issues this patch doesn't handle:
1) AVX VEX prefix length computation for -m64 isn't exact if no memory operands are
   present.  2byte VEX prefix contains just the VEX.R bit, but not VEX.B
   bit, so when VEX.B bit is needed, we need to use 3byte VEX prefix.  But
   I have no idea how to find out from the operands which operand is
   stored in vvvv field, which has extension bit in VEX.R and which has
   extension bit in VEX.B.  Only for VEX.B we should be checking whether
   it is %r8{,d}..%r15{,d} or %xmm8..%xmm15.  Examples of reported failures:
5 vmovss	%xmm10, %xmm9, %xmm8	#	*avx_loadld/3	[length = 4]
5 vpunpcklwd	%xmm8, %xmm4, %xmm0	#	*avx_punpcklwd	[length = 4]
5 vpxor	%xmm9, %xmm9, %xmm9	#	*avx_movv4si_internal/1	[length = 4]
6 vpinsrw	$1, %r8d, %xmm2, %xmm2	#	*avx_pinsrw	[length = 5]
2) %H[0-9] in patterns, in some rare cases the +8 which isn't present
   in the operand changes length_address attribute (e.g. if there is
   no displacement in the original operand, or displacement -8, or
   displacement 120, or displacement -136).  Example of reported failures:
4 movq	8(%rdi), %rax	#	*vec_extractv2di_1_rex64/4	[length = 3]
3) it seems gas optimizes away 0(%rdi) into (%rdi), not sure if it
   is allowed to do so, but perhaps gcc should try to avoid outputting the
   0 in such cases:
3 leal	0(%esp), %edi	#	*lea_1	[length = 4]
3 movzbl	0(%esi), %edi	#	*movqi_1/6	[length = 4]
4 leaq  0(%rsp), %rax   #       *lea_2_rex64    [length = 5]
4) various i387 sequences emitted using output_* routines in i386.c don't
   have exact length computed:
2 fcomip	%st(1), %st	#	*cmpfp_i_i387	[length = 4]
2 fucomip	%st(1), %st	#	*cmpfp_iu_387	[length = 4]
2 fucomi	%st(1), %st	#	*cmpfp_iu_387	[length = 4]
5) various instructions have multi/other type with the default length (16),
   that includes some i387 instructions as well as e.g. sync.md stuff:
2 fcompp	#	*cmpfp_xf	[length = 16]
2 ftst	#	*cmpfp_0	[length = 16]
2 fucompp	#	*cmpfp_u	[length = 16]
2 fucomp	%st(1)	#	*cmpfp_u	[length = 16]
2 fucom	%st(0)	#	*cmpfp_u	[length = 16]
2 xchgl	%ebx, %edi	#	*sync_double_compare_and_swapdi_pic	[length = 16]
3 fldcw	-12(%ebp)	#	fix_truncsi_i387	[length = 16]
3 fldcw	-28(%ebp)	#	fix_truncdi_i387	[length = 16]
3 movl	-28(%ebp), %ebx	#	stack_tls_protect_test_si	[length = 16]
4 lock cmpxchgl	%edx, (%esi)	#	*sync_compare_and_swapsi	[length = 16]
5 movq	8(%rsp), %rax	#	stack_tls_protect_test_di	[length = 16]
6 fldcw	-1308(%ebp)	#	fix_truncsi_i387	[length = 16]
6 lock cmpxchgq	%rdx, (%r12,%r15)	#	*sync_compare_and_swapdi	[length = 16]
6 movl	%gs:20, %eax	#	stack_tls_protect_set_si	[length = 16]
7 lock cmpxchgq	%rdx, (%r13,%r15)	#	*sync_compare_and_swapdi	[length = 16]
8 lock cmpxchg8b	sll	#	sync_double_compare_and_swapdi	[length = 16]
9 lock cmpxchg16b	m_128(%rip)	#	sync_double_compare_and_swapti	[length = 16]
9 movq	%gs:40, %rax	#	stack_tls_protect_set_di	[length = 16]
6) other sequences have multi type, but length which is just upper bound
   and not exact:
5 call	__i686.get_pc_thunk.bx	#	set_got	[length = 12]
5 call  .L1000  #       set_got [length = 12]

For 3) I guess at least the common cases where parts.disp is const0_rtx
could be handled easily (in both memory_address_length and print_operand_address).
2) could be solved by doing plus_constant on the memory operand, ugly, but could work.
4) could be handled by writing routines going along with output_*, computing the
length.  For 1) I have no idea.

Bootstrapped/regtested on i686-linux and x86_64-linux, ok for trunk?

2009-05-28  Jakub Jelinek  <jakub@redhat.com>

	* config/i386/i386.md (prefix_data16, prefix_rep): Set to 0 for
	TYPE_SSE{MULADD,4ARG,IADD1,CVT1} by default.
	(prefix_rex): For UNIT_MMX don't imply the prefix by default
	if MODE_DI.
	(prefix_extra): Default to 2 for TYPE_SSE{MULADD,4ARG} and
	to 1 for TYPE_SSE{IADD1,CVT1}.
	(prefix_vex_imm8): Removed.
	(length_vex): Only pass 1 as second argument to
	ix86_attr_length_vex_default if prefix_extra is 0.
	(modrm): For TYPE_INCDEC only set to 0 if not TARGET_64BIT.
	(length): For prefix vex computation use length_immediate
	attribute instead of prefix_vex_imm8.
	(cmpqi_ext_3_insn, cmpqi_ext_3_insn_rex64,
	addqi_ext_1, addqi_ext_1_rex64, *testqi_ext_0, andqi_ext_0,
	*andqi_ext_0_cc, *iorqi_ext_0, *xorqi_ext_0, *xorqi_cc_ext_1,
	*xorqi_cc_ext_1_rex64): Override modrm attribute to 1.
	(extendsidi2_rex64, extendhidi2, extendqidi2, extendhisi2,
	*extendhisi2_zext, extendqihi2, extendqisi2, *extendqisi2_zext): Emit
	a space in between the operands.
	(*anddi_1_rex64, *andsi_1): Likewise.  Override prefix_rex to 1
	if one operand is 0xff and the other one si, di, bp or sp.
	(*andhi_1): Override prefix_rex to 1 if one operand is 0xff and the
	other one si, di, bp or sp.
	(*btsq, *btrq, *btcq, *btdi_rex64, *btsi): Add mode attribute.
	(*ffssi_1, *ffsdi_1, ctzsi2, ctzdi2): Add
	type and mode attributes.
	(*bsr, *bsr_rex64, *bsrhi): Add type attribute.
	(*cmpfp_i_mixed, *cmpfp_iu_mixed): For TYPE_SSECOMI, clear
	prefix_rep attribute and set prefix_data16 attribute iff MODE_DF.
	(*cmpfp_i_sse, *cmpfp_iu_sse): Clear prefix_rep attribute and set
	prefix_data16 attribute iff MODE_DF.
	(*movsi_1): For TYPE_SSEMOV MODE_SI set prefix_data16 attribute.
	(fix_trunc<mode>di_sse): Set prefix_rex attribute.
	(*adddi_4_rex64, *addsi_4): Use const128_operand instead of
	constm128_operand in length_immediate computation.
	(*addhi_4): Likewise.  Fix mode attribute to MODE_HI.
	(anddi_1_rex64): Use movzbl/movzwl instead of movzbq/movzwq.
	(*avx_ashlti3, sse2_ashlti3, *avx_lshrti3, sse2_lshrti3): Set
	length_immediate attribute to 1.
	(x86_fnstsw_1, x86_fnstcw_1, x86_fldcw_1): Fix length attribute.
	(*movdi_1_rex64): Override prefix_rex or prefix_data16 attributes
	for certain alternatives.
	(*movdf_nointeger, *movdf_integer_rex64, *movdf_integer): Override
	prefix_data16 attribute if MODE_V1DF.
	(*avx_setcc<mode>, *sse_setcc<mode>, *sse5_setcc<mode>): Set
	length_immediate to 1.
	(set_got_rex64, set_rip_rex64): Remove length attribute, set
	length_address to 4, set mode attribute to MODE_DI.
	(set_got_offset_rex64): Likewise.  Set length_immediate to 0.
	(fxam<mode>2_i387): Set length attribute to 4.
	(*prefetch_sse, *prefetch_sse_rex, *prefetch_3dnow,
	*prefetch_3dnow_rex): Override length_address attribute.
	(sse4_2_crc32<mode>): Override prefix_data16 and prefix_rex
	attributes.
	* config/i386/predicates.md (ext_QIreg_nomode_operand): New predicate.
	(constm128_operand): Removed.
	* config/i386/i386.c (memory_address_length): For
	disp && !index && !base in 64-bit mode account for SIB byte if
	print_operand_address can't optimize disp32 into disp32(%rip)
	and UNSPEC doesn't imply (%rip) addressing.  Add 1 to length
	for fs: or gs: segment.
	(ix86_attr_length_immediate_default): When checking if shortform
	is possible, truncate immediate to the length of the non-shortened
	immediate.
	(ix86_attr_length_address_default): Ignore MEM_P operands
	with X constraint.
	(ix86_attr_length_vex_default): Only check for DImode on
	GENERAL_REG_P operands.
	* config/i386/sse.md (<sse>_comi, <sse>_ucomi): Clear
	prefix_rep attribute, set prefix_data16 attribute iff MODE_DF.
	(sse_cvttps2pi): Clear prefix_rep attribute.
	(sse2_cvttps2dq, *sse2_cvtpd2dq, sse2_cvtps2pd): Clear prefix_data16
	attribute.
	(*sse2_cvttpd2dq): Don't clear prefix_rep attribute.
	(*avx_ashr<mode>3, ashr<mode>3, *avx_lshr<mode>3, lshr<mode>3,
	*avx_ashl<mode>3, ashl<mode>3): Set length_immediate attribute to 1
	iff operand 2 is const_int_operand.
	(*vec_dupv4si, avx_shufpd256_1, *avx_shufpd_<mode>,
	sse2_shufpd_<mode>): Set length_immediate attribute to 1.
	(sse2_pshufd_1): Likewise.  Set prefix attribute to maybe_vex
	instead of vex.
	(sse2_pshuflw_1, sse2_pshufhw_1): Set length_immediate to 1 and clear
	prefix_data16.
	(sse2_unpckhpd, sse2_unpcklpd, sse2_storehpd, *vec_concatv2df): Set
	prefix_data16 attribute for movlpd and movhpd instructions.
	(sse2_loadhpd, sse2_loadlpd, sse2_movsd): Likewise.  Override
	length_immediate for shufpd instruction.
	(sse2_movntsi, sse3_lddqu): Clear prefix_data16 attribute.
	(avx_cmpp<avxmodesuffixf2c><mode>3,
	avx_cmps<ssemodesuffixf2c><mode>3, *avx_maskcmp<mode>3,
	<sse>_maskcmp<mode>3, <sse>_vmmaskcmp<mode>3,
	avx_shufps256_1, *avx_shufps_<mode>, sse_shufps_<mode>,
	*vec_dupv4sf_avx, *vec_dupv4sf): Set
	length_immediate attribute to 1.
	(*avx_cvtsi2ssq, *avx_cvtsi2sdq): Set length_vex attribute to 4.
	(sse_cvtsi2ssq, sse2_cvtsi2sdq): Set prefix_rex attribute to 1.
	(sse2_cvtpi2pd, sse_loadlps, sse2_storelpd): Override
	prefix_data16 attribute for the first alternative to 1.
	(*avx_loadlps): Override length_immediate for the first alternative.
	(*vec_concatv2sf_avx): Override length_immediate and prefix_extra
	attributes for second alternative.
	(*vec_concatv2sf_sse4_1): Override length_immediate and
	prefix_data16 attributes for second alternative.
	(*vec_setv4sf_avx, *avx_insertps, vec_extract_lo_<mode>,
	vec_extract_hi_<mode>, vec_extract_lo_v16hi,
	vec_extract_hi_v16hi, vec_extract_lo_v32qi,
	vec_extract_hi_v32qi): Set prefix_extra and length_immediate to 1.
	(*vec_setv4sf_sse4_1, sse4_1_insertps, *sse4_1_extractps): Set
	prefix_data16 and length_immediate to 1.
	(*avx_mulv2siv2di3, *avx_mulv4si3, sse4_2_gtv2di3): Set prefix_extra
	to 1.
	(*avx_<code><mode>3, *avx_eq<mode>3, *avx_gt<mode>3): Set
	prefix_extra attribute for variants that don't have 0f prefix
	alone.
	(*avx_pinsr<ssevecsize>): Likewise.  Set length_immediate to 1.
	(*sse4_1_pinsrb, *sse2_pinsrw, *sse4_1_pinsrd, *sse4_1_pextrb,
	*sse4_1_pextrb_memory, *sse2_pextrw, *sse4_1_pextrw_memory,
	*sse4_1_pextrd): Set length_immediate to 1.
	(*sse4_1_pinsrd): Likewise.  Set prefix_extra to 1.
	(*sse4_1_pinsrq, *sse4_1_pextrq): Set prefix_rex and length_immediate
	to 1.
	(*vec_extractv2di_1_rex64_avx, *vec_extractv2di_1_rex64,
	*vec_extractv2di_1_avx, *vec_extractv2di_1_sse2): Override
	length_immediate to 1 for second alternative.
	(*vec_concatv2si_avx, *vec_concatv2di_rex64_avx): Override
	prefix_extra and length_immediate attributes for the first
	alternative.
	(vec_concatv2si_sse4_1): Override length_immediate to 1 for the
	first alternative.
	(*vec_concatv2di_rex64_sse4_1): Likewise.  Override prefix_rex
	to 1 for the first and third alternative.
	(*vec_concatv2di_rex64_sse): Override prefix_rex to 1 for the second
	alternative.
	(*sse2_maskmovdqu, *sse2_maskmovdqu_rex64): Override length_vex
	attribute.
	(*sse_sfence, sse2_mfence, sse2_lfence): Override length_address
	attribute to 0.
	(*avx_phaddwv8hi3, *avx_phadddv4si3, *avx_phaddswv8hi3,
	*avx_phsubwv8hi3, *avx_phsubdv4si3, *avx_phsubswv8hi,
	*avx_pmaddubsw128, *avx_pmulhrswv8hi3, *avx_pshufbv16qi3,
	*avx_psign<mode>3): Set prefix_extra attribute to 1.
	(ssse3_phaddwv4hi3, ssse3_phadddv2si3, ssse3_phaddswv4hi3,
	ssse3_phsubwv4hi3, ssse3_phsubdv2si3, ssse3_phsubswv4hi3,
	ssse3_pmaddubsw, *ssse3_pmulhrswv4hi, ssse3_pshufbv8qi3,
	ssse3_psign<mode>3): Override prefix_rex attribute.
	(*avx_palignrti): Override prefix_extra and length_immediate
	to 1.
	(ssse3_palignrti): Override length_immediate to 1.
	(ssse3_palignrdi): Override length_immediate to 1, override
	prefix_rex attribute.
	(abs<mode>2): Override prefix_rep to 0, override prefix_rex
	attribute.
	(sse4a_extrqi): Override length_immediate to 2.
	(sse4a_insertqi): Likewise.  Override prefix_data16 to 0.
	(sse4a_insertq): Override prefix_data16 to 0.
	(avx_blendp<avxmodesuffixf2c><avxmodesuffix>,
	avx_blendvp<avxmodesuffixf2c><avxmodesuffix>,
	avx_dpp<avxmodesuffixf2c><avxmodesuffix>, *avx_mpsadbw,
	*avx_pblendvb, *avx_pblendw, avx_roundp<avxmodesuffixf2c>256,
	avx_rounds<avxmodesuffixf2c>256): Override prefix_extra
	and length_immediate to 1.
	(sse4_1_blendp<ssemodesuffixf2c>, sse4_1_dpp<ssemodesuffixf2c>,
	sse4_2_pcmpestr, sse4_2_pcmpestri, sse4_2_pcmpestrm,
	sse4_2_pcmpestr_cconly, sse4_2_pcmpistr, sse4_2_pcmpistri,
	sse4_2_pcmpistrm, sse4_2_pcmpistr_cconly): Override prefix_data16
	and length_immediate to 1.
	(sse4_1_blendvp<ssemodesuffixf2c>): Override prefix_data16 to 1.
	(sse4_1_mpsadbw, sse4_1_pblendw): Override length_immediate to 1.
	(*avx_packusdw, avx_vtestp<avxmodesuffixf2c><avxmodesuffix>,
	avx_ptest256): Override prefix_extra to 1.
	(sse4_1_roundp<ssemodesuffixf2c>, sse4_1_rounds<ssemodesuffixf2c>):
	Override prefix_data16 and length_immediate to 1.
	(sse5_pperm_zero_v16qi_v8hi, sse5_pperm_sign_v16qi_v8hi,
	sse5_pperm_zero_v8hi_v4si, sse5_pperm_sign_v8hi_v4si,
	sse5_pperm_zero_v4si_v2di, sse5_pperm_sign_v4si_v2di,
	sse5_vrotl<mode>3, sse5_ashl<mode>3, sse5_lshl<mode>3): Override
	prefix_data16 to 0 and prefix_extra to 2.
	(sse5_rotl<mode>3, sse5_rotr<mode>3): Override length_immediate to 1.
	(sse5_frcz<mode>2, sse5_vmfrcz<mode>2): Don't override prefix_extra
	attribute.
	(*sse5_vmmaskcmp<mode>3, sse5_com_tf<mode>3,
	sse5_maskcmp<mode>3, sse5_maskcmp<mode>3, sse5_maskcmp_uns<mode>3):
	Override prefix_data16 and prefix_rep to 0, length_immediate to 1
	and prefix_extra to 2.
	(sse5_maskcmp_uns2<mode>3, sse5_pcom_tf<mode>3): Override
	prefix_data16 to 0, length_immediate to 1 and prefix_extra to 2.
	(*avx_aesenc, *avx_aesenclast, *avx_aesdec, *avx_aesdeclast,
	avx_vpermilvar<mode>3,
	avx_vbroadcasts<avxmodesuffixf2c><avxmodesuffix>,
	avx_vbroadcastss256, avx_vbroadcastf128_p<avxmodesuffixf2c>256,
	avx_maskloadp<avxmodesuffixf2c><avxmodesuffix>,
	avx_maskstorep<avxmodesuffixf2c><avxmodesuffix>):
	Override prefix_extra to 1.
	(aeskeygenassist, pclmulqdq): Override length_immediate to 1.
	(*vpclmulqdq, avx_vpermil<mode>, avx_vperm2f128<mode>3,
	vec_set_lo_<mode>, vec_set_hi_<mode>, vec_set_lo_v16hi,
	vec_set_hi_v16hi, vec_set_lo_v32qi, vec_set_hi_v32qi): Override
	prefix_extra and length_immediate to 1.
	(*avx_vzeroall, avx_vzeroupper, avx_vzeroupper_rex64): Override
	modrm to 0.
	(*vec_concat<mode>_avx): Override prefix_extra and length_immediate
	to 1 for the first alternative.
	* config/i386/mmx.md (*mov<mode>_internal_rex64): Override
	prefix_rep, prefix_data16 and/or prefix_rex attributes in certain
	cases.
	(*mov<mode>_internal_avx, *movv2sf_internal_rex64,
	*movv2sf_internal_avx, *movv2sf_internal): Override
	prefix_rep attribute for certain alternatives.
	(*mov<mode>_internal): Override prefix_rep or prefix_data16
	attributes for certain alternatives.
	(*movv2sf_internal_rex64_avx): Override prefix_rep and length_vex
	attributes for certain alternatives.
	(*mmx_addv2sf3, *mmx_subv2sf3, *mmx_mulv2sf3,
	*mmx_<code>v2sf3_finite, *mmx_<code>v2sf3, mmx_rcpv2sf2,
	mmx_rcpit1v2sf3, mmx_rcpit2v2sf3, mmx_rsqrtv2sf2, mmx_rsqit1v2sf3,
	mmx_haddv2sf3, mmx_hsubv2sf3, mmx_addsubv2sf3,
	*mmx_eqv2sf3, mmx_gtv2sf3, mmx_gev2sf3, mmx_pf2id, mmx_pf2iw,
	mmx_pi2fw, mmx_floatv2si2, mmx_pswapdv2sf2, *mmx_pmulhrwv4hi3,
	mmx_pswapdv2si2): Set prefix_extra attribute to 1.
	(mmx_ashr<mode>3, mmx_lshr<mode>3, mmx_ashl<mode>3): Set
	length_immediate to 1 if operand 2 is const_int_operand.
	(*mmx_pinsrw, mmx_pextrw, mmx_pshufw_1, *vec_dupv4hi,
	*vec_extractv2si_1): Set length_immediate
	attribute to 1.
	(*mmx_uavgv8qi3): Override prefix_extra attribute to 1 if
	using old 3DNOW insn rather than SSE/3DNOW_A.
	(mmx_emms, mmx_femms): Clear modrm attribute.

--- gcc/config/i386/i386.md.jj	2009-05-25 11:30:13.000000000 +0200
+++ gcc/config/i386/i386.md	2009-05-28 10:38:03.000000000 +0200
@@ -416,16 +416,23 @@ (define_attr "length_address" ""
 
 ;; Set when length prefix is used.
 (define_attr "prefix_data16" ""
-  (if_then_else (ior (eq_attr "mode" "HI")
-		     (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF,TI")))
-    (const_int 1)
-    (const_int 0)))
+  (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
+	   (const_int 0)
+	 (eq_attr "mode" "HI")
+	   (const_int 1)
+	 (and (eq_attr "unit" "sse") (eq_attr "mode" "V2DF,TI"))
+	   (const_int 1)
+	]
+	(const_int 0)))
 
 ;; Set when string REP prefix is used.
 (define_attr "prefix_rep" ""
-  (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
-    (const_int 1)
-    (const_int 0)))
+  (cond [(eq_attr "type" "ssemuladd,sse4arg,sseiadd1,ssecvt1")
+	   (const_int 0)
+	 (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
+	   (const_int 1)
+	]
+	(const_int 0)))
 
 ;; Set when 0f opcode prefix is used.
 (define_attr "prefix_0f" ""
@@ -440,7 +447,8 @@ (define_attr "prefix_rex" ""
   (cond [(ne (symbol_ref "!TARGET_64BIT") (const_int 0))
 	   (const_int 0)
 	 (and (eq_attr "mode" "DI")
-  	      (eq_attr "type" "!push,pop,call,callv,leave,ibr"))
+	      (and (eq_attr "type" "!push,pop,call,callv,leave,ibr")
+		   (eq_attr "unit" "!mmx")))
 	   (const_int 1)
 	 (and (eq_attr "mode" "QI")
 	      (ne (symbol_ref "x86_extended_QIreg_mentioned_p (insn)")
@@ -455,8 +463,17 @@ (define_attr "prefix_rex" ""
 	]
 	(const_int 0)))
 
-;; There are also additional prefixes in SSSE3.
-(define_attr "prefix_extra" "" (const_int 0))
+;; There are also additional prefixes in 3DNOW, SSSE3 or SSE5.
+;; ssemuladd,sse4arg default to 0f24/0f25 and DREX byte,
+;; sseiadd1,ssecvt1 to 0f7a with no DREX byte.
+;; 3DNOW has 0f0f prefix, SSSE3 and SSE4_{1,2} 0f38/0f3a.
+(define_attr "prefix_extra" ""
+  (cond [(eq_attr "type" "ssemuladd,sse4arg")
+	   (const_int 2)
+	 (eq_attr "type" "sseiadd1,ssecvt1")
+	   (const_int 1)
+	]
+	(const_int 0)))
 
 ;; Prefix used: original, VEX or maybe VEX.
 (define_attr "prefix" "orig,vex,maybe_vex"
@@ -464,15 +481,16 @@ (define_attr "prefix" "orig,vex,maybe_ve
     (const_string "vex")
     (const_string "orig")))
 
-;; There is a 8bit immediate for VEX.
-(define_attr "prefix_vex_imm8" "" (const_int 0))
-
 ;; VEX W bit is used.
 (define_attr "prefix_vex_w" "" (const_int 0))
 
 ;; The length of VEX prefix
+;; Only instructions with 0f prefix can have 2 byte VEX prefix,
+;; 0f38/0f3a prefixes can't.  In i386.md 0f3[8a] is
+;; still prefix_0f 1, with prefix_extra 1.
 (define_attr "length_vex" ""
-  (if_then_else (eq_attr "prefix_0f" "1")
+  (if_then_else (and (eq_attr "prefix_0f" "1")
+		     (eq_attr "prefix_extra" "0"))
     (if_then_else (eq_attr "prefix_vex_w" "1")
       (symbol_ref "ix86_attr_length_vex_default (insn, 1, 1)")
       (symbol_ref "ix86_attr_length_vex_default (insn, 1, 0)"))
@@ -487,8 +505,9 @@ (define_attr "modrm" ""
 	 (eq_attr "unit" "i387")
 	   (const_int 0)
          (and (eq_attr "type" "incdec")
-	      (ior (match_operand:SI 1 "register_operand" "")
-		   (match_operand:HI 1 "register_operand" "")))
+	      (and (eq (symbol_ref "TARGET_64BIT") (const_int 0))
+		   (ior (match_operand:SI 1 "register_operand" "")
+			(match_operand:HI 1 "register_operand" ""))))
 	   (const_int 0)
 	 (and (eq_attr "type" "push")
 	      (not (match_operand 1 "memory_operand" "")))
@@ -534,7 +553,7 @@ (define_attr "length" ""
 	      (and (eq_attr "prefix" "maybe_vex")
 		    (ne (symbol_ref "TARGET_AVX") (const_int 0))))
 	   (plus (attr "length_vex")
-		 (plus (attr "prefix_vex_imm8")
+		 (plus (attr "length_immediate")
 		       (plus (attr "modrm")
 			     (attr "length_address"))))]
 	 (plus (plus (attr "modrm")
@@ -1155,6 +1174,7 @@ (define_insn "cmpqi_ext_3_insn"
   "!TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
   "cmp{b}\t{%1, %h0|%h0, %1}"
   [(set_attr "type" "icmp")
+   (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
 
 (define_insn "cmpqi_ext_3_insn_rex64"
@@ -1169,6 +1189,7 @@ (define_insn "cmpqi_ext_3_insn_rex64"
   "TARGET_64BIT && ix86_match_ccmode (insn, CCmode)"
   "cmp{b}\t{%1, %h0|%h0, %1}"
   [(set_attr "type" "icmp")
+   (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
 
 (define_insn "*cmpqi_ext_4"
@@ -1516,7 +1537,7 @@ (define_insn "x86_fnstsw_1"
 	(unspec:HI [(reg:CCFP FPSR_REG)] UNSPEC_FNSTSW))]
   "TARGET_80387"
   "fnstsw\t%0"
-  [(set_attr "length" "2")
+  [(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
    (set_attr "mode" "SI")
    (set_attr "unit" "i387")])
 
@@ -1556,6 +1577,17 @@ (define_insn "*cmpfp_i_mixed"
      (if_then_else (match_operand:SF 1 "" "")
         (const_string "SF")
         (const_string "DF")))
+   (set (attr "prefix_rep")
+	(if_then_else (eq_attr "type" "ssecomi")
+		      (const_string "0")
+		      (const_string "*")))
+   (set (attr "prefix_data16")
+	(cond [(eq_attr "type" "fcmp")
+		 (const_string "*")
+	       (eq_attr "mode" "DF")
+		 (const_string "1")
+	      ]
+	      (const_string "0")))
    (set_attr "athlon_decode" "vector")
    (set_attr "amdfam10_decode" "direct")])
 
@@ -1573,6 +1605,11 @@ (define_insn "*cmpfp_i_sse"
      (if_then_else (match_operand:SF 1 "" "")
         (const_string "SF")
         (const_string "DF")))
+   (set_attr "prefix_rep" "0")
+   (set (attr "prefix_data16")
+	(if_then_else (eq_attr "mode" "DF")
+		      (const_string "1")
+		      (const_string "0")))
    (set_attr "athlon_decode" "vector")
    (set_attr "amdfam10_decode" "direct")])
 
@@ -1610,6 +1647,17 @@ (define_insn "*cmpfp_iu_mixed"
      (if_then_else (match_operand:SF 1 "" "")
         (const_string "SF")
         (const_string "DF")))
+   (set (attr "prefix_rep")
+	(if_then_else (eq_attr "type" "ssecomi")
+		      (const_string "0")
+		      (const_string "*")))
+   (set (attr "prefix_data16")
+	(cond [(eq_attr "type" "fcmp")
+		 (const_string "*")
+	       (eq_attr "mode" "DF")
+		 (const_string "1")
+	      ]
+	      (const_string "0")))
    (set_attr "athlon_decode" "vector")
    (set_attr "amdfam10_decode" "direct")])
 
@@ -1627,6 +1675,11 @@ (define_insn "*cmpfp_iu_sse"
      (if_then_else (match_operand:SF 1 "" "")
         (const_string "SF")
         (const_string "DF")))
+   (set_attr "prefix_rep" "0")
+   (set (attr "prefix_data16")
+	(if_then_else (eq_attr "mode" "DF")
+		      (const_string "1")
+		      (const_string "0")))
    (set_attr "athlon_decode" "vector")
    (set_attr "amdfam10_decode" "direct")])
 
@@ -1802,6 +1855,10 @@ (define_insn "*movsi_1"
      (if_then_else (eq_attr "alternative" "0,1,2,3,4,5")
        (const_string "orig")
        (const_string "maybe_vex")))
+   (set (attr "prefix_data16")
+     (if_then_else (and (eq_attr "type" "ssemov") (eq_attr "mode" "SI"))
+       (const_string "1")
+       (const_string "*")))
    (set (attr "mode")
      (cond [(eq_attr "alternative" "2,3")
 	      (const_string "DI")
@@ -2651,6 +2708,8 @@ (define_insn "*movdi_1_rex64"
        (and (eq_attr "alternative" "2") (eq_attr "type" "imov"))
 	 (const_string "8")
 	 (const_string "*")))
+   (set_attr "prefix_rex" "*,*,*,*,*,*,*,1,*,1,*,*,*,*,*,*,*,*,*")
+   (set_attr "prefix_data16" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,1,*,*,*")
    (set (attr "prefix")
      (if_then_else (eq_attr "alternative" "11,12,13,14,15,16")
        (const_string "maybe_vex")
@@ -3235,6 +3294,10 @@ (define_insn "*movdf_nointeger"
      (if_then_else (eq_attr "alternative" "0,1,2,3,4")
        (const_string "orig")
        (const_string "maybe_vex")))
+   (set (attr "prefix_data16")
+     (if_then_else (eq_attr "mode" "V1DF")
+       (const_string "1")
+       (const_string "*")))
    (set (attr "mode")
         (cond [(eq_attr "alternative" "0,1,2")
 		 (const_string "DF")
@@ -3369,6 +3432,10 @@ (define_insn "*movdf_integer_rex64"
      (if_then_else (eq_attr "alternative" "0,1,2,3,4")
        (const_string "orig")
        (const_string "maybe_vex")))
+   (set (attr "prefix_data16")
+     (if_then_else (eq_attr "mode" "V1DF")
+       (const_string "1")
+       (const_string "*")))
    (set (attr "mode")
         (cond [(eq_attr "alternative" "0,1,2")
 		 (const_string "DF")
@@ -3489,6 +3556,10 @@ (define_insn "*movdf_integer"
     }
 }
   [(set_attr "type" "fmov,fmov,fmov,multi,multi,sselog1,ssemov,ssemov,ssemov")
+   (set (attr "prefix_data16")
+     (if_then_else (eq_attr "mode" "V1DF")
+       (const_string "1")
+       (const_string "*")))
    (set (attr "mode")
         (cond [(eq_attr "alternative" "0,1,2")
 		 (const_string "DF")
@@ -4194,7 +4265,7 @@ (define_insn "extendsidi2_rex64"
   "TARGET_64BIT"
   "@
    {cltq|cdqe}
-   movs{lq|x}\t{%1,%0|%0, %1}"
+   movs{lq|x}\t{%1, %0|%0, %1}"
   [(set_attr "type" "imovx")
    (set_attr "mode" "DI")
    (set_attr "prefix_0f" "0")
@@ -4204,7 +4275,7 @@ (define_insn "extendhidi2"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
   "TARGET_64BIT"
-  "movs{wq|x}\t{%1,%0|%0, %1}"
+  "movs{wq|x}\t{%1, %0|%0, %1}"
   [(set_attr "type" "imovx")
    (set_attr "mode" "DI")])
 
@@ -4212,7 +4283,7 @@ (define_insn "extendqidi2"
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
   "TARGET_64BIT"
-  "movs{bq|x}\t{%1,%0|%0, %1}"
+  "movs{bq|x}\t{%1, %0|%0, %1}"
    [(set_attr "type" "imovx")
     (set_attr "mode" "DI")])
 
@@ -4300,7 +4371,7 @@ (define_insn "extendhisi2"
     case 0:
       return "{cwtl|cwde}";
     default:
-      return "movs{wl|x}\t{%1,%0|%0, %1}";
+      return "movs{wl|x}\t{%1, %0|%0, %1}";
     }
 }
   [(set_attr "type" "imovx")
@@ -4327,7 +4398,7 @@ (define_insn "*extendhisi2_zext"
     case 0:
       return "{cwtl|cwde}";
     default:
-      return "movs{wl|x}\t{%1,%k0|%k0, %1}";
+      return "movs{wl|x}\t{%1, %k0|%k0, %1}";
     }
 }
   [(set_attr "type" "imovx")
@@ -4353,7 +4424,7 @@ (define_insn "extendqihi2"
     case 0:
       return "{cbtw|cbw}";
     default:
-      return "movs{bw|x}\t{%1,%0|%0, %1}";
+      return "movs{bw|x}\t{%1, %0|%0, %1}";
     }
 }
   [(set_attr "type" "imovx")
@@ -4373,7 +4444,7 @@ (define_insn "extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
   ""
-  "movs{bl|x}\t{%1,%0|%0, %1}"
+  "movs{bl|x}\t{%1, %0|%0, %1}"
    [(set_attr "type" "imovx")
     (set_attr "mode" "SI")])
 
@@ -4382,7 +4453,7 @@ (define_insn "*extendqisi2_zext"
 	(zero_extend:DI
 	  (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm"))))]
   "TARGET_64BIT"
-  "movs{bl|x}\t{%1,%k0|%k0, %1}"
+  "movs{bl|x}\t{%1, %k0|%k0, %1}"
    [(set_attr "type" "imovx")
     (set_attr "mode" "SI")])
 
@@ -4994,6 +5065,7 @@ (define_insn "fix_trunc<mode>di_sse"
   "%vcvtts<ssemodefsuffix>2si{q}\t{%1, %0|%0, %1}"
   [(set_attr "type" "sseicvt")
    (set_attr "prefix" "maybe_vex")
+   (set_attr "prefix_rex" "1")
    (set_attr "mode" "<MODE>")
    (set_attr "athlon_decode" "double,vector")
    (set_attr "amdfam10_decode" "double,double")])
@@ -5268,7 +5340,7 @@ (define_insn "x86_fnstcw_1"
 	(unspec:HI [(reg:HI FPCR_REG)] UNSPEC_FSTCW))]
   "TARGET_80387"
   "fnstcw\t%0"
-  [(set_attr "length" "2")
+  [(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
    (set_attr "mode" "HI")
    (set_attr "unit" "i387")])
 
@@ -5277,7 +5349,7 @@ (define_insn "x86_fldcw_1"
 	(unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
   "TARGET_80387"
   "fldcw\t%0"
-  [(set_attr "length" "2")
+  [(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
    (set_attr "mode" "HI")
    (set_attr "unit" "i387")
    (set_attr "athlon_decode" "vector")
@@ -6650,7 +6722,7 @@ (define_insn "*adddi_4_rex64"
 	(const_string "alu")))
    (set (attr "length_immediate")
       (if_then_else
-	(and (eq_attr "type" "alu") (match_operand 2 "constm128_operand" ""))
+	(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
 	(const_string "1")
 	(const_string "*")))
    (set_attr "mode" "DI")])
@@ -7121,7 +7193,7 @@ (define_insn "*addsi_4"
 	(const_string "alu")))
    (set (attr "length_immediate")
       (if_then_else
-	(and (eq_attr "type" "alu") (match_operand 2 "constm128_operand" ""))
+	(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
 	(const_string "1")
 	(const_string "*")))
    (set_attr "mode" "SI")])
@@ -7409,10 +7481,10 @@ (define_insn "*addhi_4"
 	(const_string "alu")))
    (set (attr "length_immediate")
       (if_then_else
-	(and (eq_attr "type" "alu") (match_operand 2 "constm128_operand" ""))
+	(and (eq_attr "type" "alu") (match_operand 2 "const128_operand" ""))
 	(const_string "1")
 	(const_string "*")))
-   (set_attr "mode" "SI")])
+   (set_attr "mode" "HI")])
 
 
 (define_insn "*addhi_5"
@@ -7808,6 +7880,7 @@ (define_insn "addqi_ext_1"
      (if_then_else (match_operand:QI 2 "incdec_operand" "")
 	(const_string "incdec")
 	(const_string "alu")))
+   (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
 
 (define_insn "*addqi_ext_1_rex64"
@@ -7844,6 +7917,7 @@ (define_insn "*addqi_ext_1_rex64"
      (if_then_else (match_operand:QI 2 "incdec_operand" "")
 	(const_string "incdec")
 	(const_string "alu")))
+   (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
 
 (define_insn "*addqi_ext_2"
@@ -9308,6 +9382,7 @@ (define_insn "*testqi_ext_0"
   [(set_attr "type" "test")
    (set_attr "mode" "QI")
    (set_attr "length_immediate" "1")
+   (set_attr "modrm" "1")
    (set_attr "pent_pair" "np")])
 
 (define_insn "*testqi_ext_1"
@@ -9559,9 +9634,9 @@ (define_insn "*anddi_1_rex64"
 
 	operands[1] = gen_lowpart (mode, operands[1]);
 	if (mode == QImode)
-	  return "movz{bq|x}\t{%1,%0|%0, %1}";
+	  return "movz{bl|x}\t{%1, %k0|%k0, %1}";
 	else
-	  return "movz{wq|x}\t{%1,%0|%0, %1}";
+	  return "movz{wl|x}\t{%1, %k0|%k0, %1}";
       }
 
     default:
@@ -9574,7 +9649,14 @@ (define_insn "*anddi_1_rex64"
 }
   [(set_attr "type" "alu,alu,alu,imovx")
    (set_attr "length_immediate" "*,*,*,0")
-   (set_attr "mode" "SI,DI,DI,DI")])
+   (set (attr "prefix_rex")
+     (if_then_else
+       (and (eq_attr "type" "imovx")
+	    (and (ne (symbol_ref "INTVAL (operands[2]) == 0xff") (const_int 0))
+		 (match_operand 1 "ext_QIreg_nomode_operand" "")))
+       (const_string "1")
+       (const_string "*")))
+   (set_attr "mode" "SI,DI,DI,SI")])
 
 (define_insn "*anddi_2"
   [(set (reg FLAGS_REG)
@@ -9623,9 +9705,9 @@ (define_insn "*andsi_1"
 
 	operands[1] = gen_lowpart (mode, operands[1]);
 	if (mode == QImode)
-	  return "movz{bl|x}\t{%1,%0|%0, %1}";
+	  return "movz{bl|x}\t{%1, %0|%0, %1}";
 	else
-	  return "movz{wl|x}\t{%1,%0|%0, %1}";
+	  return "movz{wl|x}\t{%1, %0|%0, %1}";
       }
 
     default:
@@ -9634,6 +9716,13 @@ (define_insn "*andsi_1"
     }
 }
   [(set_attr "type" "alu,alu,imovx")
+   (set (attr "prefix_rex")
+     (if_then_else
+       (and (eq_attr "type" "imovx")
+	    (and (ne (symbol_ref "INTVAL (operands[2]) == 0xff") (const_int 0))
+		 (match_operand 1 "ext_QIreg_nomode_operand" "")))
+       (const_string "1")
+       (const_string "*")))
    (set_attr "length_immediate" "*,*,0")
    (set_attr "mode" "SI")])
 
@@ -9742,6 +9831,12 @@ (define_insn "*andhi_1"
 }
   [(set_attr "type" "alu,alu,imovx")
    (set_attr "length_immediate" "*,*,0")
+   (set (attr "prefix_rex")
+     (if_then_else
+       (and (eq_attr "type" "imovx")
+	    (match_operand 1 "ext_QIreg_nomode_operand" ""))
+       (const_string "1")
+       (const_string "*")))
    (set_attr "mode" "HI,HI,SI")])
 
 (define_insn "*andhi_2"
@@ -9861,6 +9956,7 @@ (define_insn "andqi_ext_0"
   "and{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
    (set_attr "length_immediate" "1")
+   (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
 
 ;; Generated by peephole translating test to and.  This shows up
@@ -9889,6 +9985,7 @@ (define_insn "*andqi_ext_0_cc"
   "and{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
    (set_attr "length_immediate" "1")
+   (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
 
 (define_insn "*andqi_ext_1"
@@ -10263,6 +10360,7 @@ (define_insn "*iorqi_ext_0"
   "or{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
    (set_attr "length_immediate" "1")
+   (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
 
 (define_insn "*iorqi_ext_1"
@@ -10593,6 +10691,7 @@ (define_insn "*xorqi_ext_0"
   "xor{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
    (set_attr "length_immediate" "1")
+   (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
 
 (define_insn "*xorqi_ext_1"
@@ -10711,6 +10810,7 @@ (define_insn "*xorqi_cc_ext_1"
   "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
   "xor{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
+   (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
 
 (define_insn "*xorqi_cc_ext_1_rex64"
@@ -10732,6 +10832,7 @@ (define_insn "*xorqi_cc_ext_1_rex64"
   "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
   "xor{b}\t{%2, %h0|%h0, %2}"
   [(set_attr "type" "alu")
+   (set_attr "modrm" "1")
    (set_attr "mode" "QI")])
 
 (define_expand "xorqi_cc_ext_1"
@@ -11534,6 +11635,7 @@ (define_insn "*avx_ashlti3"
 }
   [(set_attr "type" "sseishft")
    (set_attr "prefix" "vex")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_insn "sse2_ashlti3"
@@ -11547,6 +11649,7 @@ (define_insn "sse2_ashlti3"
 }
   [(set_attr "type" "sseishft")
    (set_attr "prefix_data16" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_insn "*ashlti3_1"
@@ -13386,6 +13489,7 @@ (define_insn "*avx_lshrti3"
 }
   [(set_attr "type" "sseishft")
    (set_attr "prefix" "vex")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_insn "sse2_lshrti3"
@@ -13399,6 +13503,7 @@ (define_insn "sse2_lshrti3"
 }
   [(set_attr "type" "sseishft")
    (set_attr "prefix_data16" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_insn "*lshrti3_1"
@@ -14471,7 +14576,8 @@ (define_insn "*btsq"
   "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
   "bts{q}\t{%1, %0|%0, %1}"
   [(set_attr "type" "alu1")
-   (set_attr "prefix_0f" "1")])
+   (set_attr "prefix_0f" "1")
+   (set_attr "mode" "DI")])
 
 (define_insn "*btrq"
   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
@@ -14482,7 +14588,8 @@ (define_insn "*btrq"
   "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
   "btr{q}\t{%1, %0|%0, %1}"
   [(set_attr "type" "alu1")
-   (set_attr "prefix_0f" "1")])
+   (set_attr "prefix_0f" "1")
+   (set_attr "mode" "DI")])
 
 (define_insn "*btcq"
   [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
@@ -14493,7 +14600,8 @@ (define_insn "*btcq"
   "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
   "btc{q}\t{%1, %0|%0, %1}"
   [(set_attr "type" "alu1")
-   (set_attr "prefix_0f" "1")])
+   (set_attr "prefix_0f" "1")
+   (set_attr "mode" "DI")])
 
 ;; Allow Nocona to avoid these instructions if a register is available.
 
@@ -14605,7 +14713,8 @@ (define_insn "*btdi_rex64"
   "TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))"
   "bt{q}\t{%1, %0|%0, %1}"
   [(set_attr "type" "alu1")
-   (set_attr "prefix_0f" "1")])
+   (set_attr "prefix_0f" "1")
+   (set_attr "mode" "DI")])
 
 (define_insn "*btsi"
   [(set (reg:CCC FLAGS_REG)
@@ -14618,7 +14727,8 @@ (define_insn "*btsi"
   "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
   "bt{l}\t{%1, %0|%0, %1}"
   [(set_attr "type" "alu1")
-   (set_attr "prefix_0f" "1")])
+   (set_attr "prefix_0f" "1")
+   (set_attr "mode" "SI")])
 
 ;; Store-flag instructions.
 
@@ -14731,6 +14841,7 @@ (define_insn "*avx_setcc<mode>"
   "vcmp%D1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "ssecmp")
    (set_attr "prefix" "vex")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*sse_setcc<mode>"
@@ -14741,6 +14852,7 @@ (define_insn "*sse_setcc<mode>"
   "SSE_FLOAT_MODE_P (<MODE>mode) && !TARGET_SSE5"
   "cmp%D1s<ssemodefsuffix>\t{%3, %0|%0, %3}"
   [(set_attr "type" "ssecmp")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "*sse5_setcc<mode>"
@@ -14751,6 +14863,7 @@ (define_insn "*sse5_setcc<mode>"
   "TARGET_SSE5"
   "com%Y1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "sse4arg")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "<MODE>")])
 
 
@@ -15846,7 +15959,8 @@ (define_insn "set_got_rex64"
   "TARGET_64BIT"
   "lea{q}\t{_GLOBAL_OFFSET_TABLE_(%%rip), %0|%0, _GLOBAL_OFFSET_TABLE_[rip]}"
   [(set_attr "type" "lea")
-   (set_attr "length" "6")])
+   (set_attr "length_address" "4")
+   (set_attr "mode" "DI")])
 
 (define_insn "set_rip_rex64"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -15854,7 +15968,8 @@ (define_insn "set_rip_rex64"
   "TARGET_64BIT"
   "lea{q}\t{%l1(%%rip), %0|%0, %l1[rip]}"
   [(set_attr "type" "lea")
-   (set_attr "length" "6")])
+   (set_attr "length_address" "4")
+   (set_attr "mode" "DI")])
 
 (define_insn "set_got_offset_rex64"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -15864,7 +15979,9 @@ (define_insn "set_got_offset_rex64"
   "TARGET_64BIT"
   "movabs{q}\t{$_GLOBAL_OFFSET_TABLE_-%l1, %0|%0, OFFSET FLAT:_GLOBAL_OFFSET_TABLE_-%l1}"
   [(set_attr "type" "imov")
-   (set_attr "length" "11")])
+   (set_attr "length_immediate" "0")
+   (set_attr "length_address" "8")
+   (set_attr "mode" "DI")])
 
 (define_expand "epilogue"
   [(const_int 0)]
@@ -15987,7 +16104,9 @@ (define_insn "*ffssi_1"
 	(ctz:SI (match_dup 1)))]
   ""
   "bsf{l}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_0f" "1")])
+  [(set_attr "type" "alu1")
+   (set_attr "prefix_0f" "1")
+   (set_attr "mode" "SI")])
 
 (define_expand "ffsdi2"
   [(set (match_dup 2) (const_int -1))
@@ -16013,7 +16132,9 @@ (define_insn "*ffsdi_1"
 	(ctz:DI (match_dup 1)))]
   "TARGET_64BIT"
   "bsf{q}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_0f" "1")])
+  [(set_attr "type" "alu1")
+   (set_attr "prefix_0f" "1")
+   (set_attr "mode" "DI")])
 
 (define_insn "ctzsi2"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -16021,7 +16142,9 @@ (define_insn "ctzsi2"
    (clobber (reg:CC FLAGS_REG))]
   ""
   "bsf{l}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_0f" "1")])
+  [(set_attr "type" "alu1")
+   (set_attr "prefix_0f" "1")
+   (set_attr "mode" "SI")])
 
 (define_insn "ctzdi2"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -16029,7 +16152,9 @@ (define_insn "ctzdi2"
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT"
   "bsf{q}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_0f" "1")])
+  [(set_attr "type" "alu1")
+   (set_attr "prefix_0f" "1")
+   (set_attr "mode" "DI")])
 
 (define_expand "clzsi2"
   [(parallel
@@ -16066,7 +16191,8 @@ (define_insn "*bsr"
    (clobber (reg:CC FLAGS_REG))]
   ""
   "bsr{l}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_0f" "1")
+  [(set_attr "type" "alu1")
+   (set_attr "prefix_0f" "1")
    (set_attr "mode" "SI")])
 
 (define_insn "popcount<mode>2"
@@ -16250,7 +16376,8 @@ (define_insn "*bsr_rex64"
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT"
   "bsr{q}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_0f" "1")
+  [(set_attr "type" "alu1")
+   (set_attr "prefix_0f" "1")
    (set_attr "mode" "DI")])
 
 (define_expand "clzhi2"
@@ -16288,7 +16415,8 @@ (define_insn "*bsrhi"
    (clobber (reg:CC FLAGS_REG))]
   ""
   "bsr{w}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_0f" "1")
+  [(set_attr "type" "alu1")
+   (set_attr "prefix_0f" "1")
    (set_attr "mode" "HI")])
 
 (define_expand "paritydi2"
@@ -19388,6 +19516,7 @@ (define_insn "fxam<mode>2_i387"
   "TARGET_USE_FANCY_MATH_387"
   "fxam\n\tfnstsw\t%0"
   [(set_attr "type" "multi")
+   (set_attr "length" "4")
    (set_attr "unit" "i387")
    (set_attr "mode" "<MODE>")])
 
@@ -22341,6 +22470,7 @@ (define_insn "*prefetch_sse"
 }
   [(set_attr "type" "sse")
    (set_attr "atom_sse_attr" "prefetch")
+   (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
    (set_attr "memory" "none")])
 
 (define_insn "*prefetch_sse_rex"
@@ -22360,6 +22490,7 @@ (define_insn "*prefetch_sse_rex"
 }
   [(set_attr "type" "sse")
    (set_attr "atom_sse_attr" "prefetch")
+   (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
    (set_attr "memory" "none")])
 
 (define_insn "*prefetch_3dnow"
@@ -22374,6 +22505,7 @@ (define_insn "*prefetch_3dnow"
     return "prefetchw\t%a0";
 }
   [(set_attr "type" "mmx")
+   (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
    (set_attr "memory" "none")])
 
 (define_insn "*prefetch_3dnow_rex"
@@ -22388,6 +22520,7 @@ (define_insn "*prefetch_3dnow_rex"
     return "prefetchw\t%a0";
 }
   [(set_attr "type" "mmx")
+   (set (attr "length_address") (symbol_ref "memory_address_length (operands[0])"))
    (set_attr "memory" "none")])
 
 (define_expand "stack_protect_set"
@@ -22545,6 +22678,14 @@ (define_insn "sse4_2_crc32<mode>"
   [(set_attr "type" "sselog1")
    (set_attr "prefix_rep" "1")
    (set_attr "prefix_extra" "1")
+   (set (attr "prefix_data16")
+     (if_then_else (match_operand:HI 2 "" "")
+       (const_string "1")
+       (const_string "*")))
+   (set (attr "prefix_rex")
+     (if_then_else (match_operand:QI 2 "ext_QIreg_operand" "")
+       (const_string "1")
+       (const_string "*")))
    (set_attr "mode" "SI")])
 
 (define_insn "sse4_2_crc32di"
--- gcc/config/i386/mmx.md.jj	2009-03-04 20:06:31.000000000 +0100
+++ gcc/config/i386/mmx.md	2009-05-28 10:02:04.000000000 +0200
@@ -1,5 +1,5 @@
 ;; GCC machine description for MMX and 3dNOW! instructions
-;; Copyright (C) 2005, 2007, 2008
+;; Copyright (C) 2005, 2007, 2008, 2009
 ;; Free Software Foundation, Inc.
 ;;
 ;; This file is part of GCC.
@@ -85,6 +85,12 @@ (define_insn "*mov<mode>_internal_rex64"
     %vmovq\t{%1, %0|%0, %1}"
   [(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,ssemov")
    (set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*")
+   (set_attr "prefix_rep" "*,*,*,*,*,1,1,*,1,*,*,*")
+   (set_attr "prefix_data16" "*,*,*,*,*,*,*,*,*,1,1,1")
+   (set (attr "prefix_rex")
+     (if_then_else (eq_attr "alternative" "8,9")
+       (symbol_ref "x86_extended_reg_mentioned_p (insn)")
+       (const_string "*")))
    (set (attr "prefix")
      (if_then_else (eq_attr "alternative" "7,8,9,10,11")
        (const_string "maybe_vex")
@@ -111,6 +117,7 @@ (define_insn "*mov<mode>_internal_avx"
     #"
   [(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,*,*")
    (set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*")
+   (set_attr "prefix_rep" "*,*,*,1,1,*,*,*,*,*")
    (set (attr "prefix")
      (if_then_else (eq_attr "alternative" "5,6,7")
        (const_string "vex")
@@ -141,6 +148,8 @@ (define_insn "*mov<mode>_internal"
     #"
   [(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,sselog1,ssemov,ssemov,ssemov,*,*")
    (set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*,*,*,*")
+   (set_attr "prefix_rep" "*,*,*,1,1,*,1,*,*,*,*,*,*,*")
+   (set_attr "prefix_data16" "*,*,*,*,*,*,*,1,*,*,*,*,*,*")
    (set_attr "mode" "DI,DI,DI,DI,DI,TI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
 
 (define_expand "movv2sf"
@@ -175,6 +184,8 @@ (define_insn "*movv2sf_internal_rex64_av
     vmovq\t{%1, %0|%0, %1}"
   [(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,sselog1,ssemov,ssemov,ssemov,ssemov")
    (set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*,*")
+   (set_attr "prefix_rep" "*,*,*,*,*,1,1,*,*,*,*,*,*")
+   (set_attr "length_vex" "*,*,*,*,*,*,*,*,*,*,*,4,4")
    (set (attr "prefix")
      (if_then_else (eq_attr "alternative" "7,8,9,10,11,12")
        (const_string "vex")
@@ -204,6 +215,7 @@ (define_insn "*movv2sf_internal_rex64"
     movd\t{%1, %0|%0, %1}"
   [(set_attr "type" "imov,imov,mmx,mmxmov,mmxmov,ssecvt,ssecvt,ssemov,sselog1,ssemov,ssemov,ssemov,ssemov")
    (set_attr "unit" "*,*,*,*,*,mmx,mmx,*,*,*,*,*,*")
+   (set_attr "prefix_rep" "*,*,*,*,*,1,1,*,*,*,*,*,*")
    (set_attr "mode" "DI,DI,DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
 
 (define_insn "*movv2sf_internal_avx"
@@ -227,6 +239,7 @@ (define_insn "*movv2sf_internal_avx"
     #"
   [(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,*,*")
    (set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*")
+   (set_attr "prefix_rep" "*,*,*,1,1,*,*,*,*,*,*")
    (set (attr "prefix")
      (if_then_else (eq_attr "alternative" "5,6,7,8")
        (const_string "vex")
@@ -254,6 +267,7 @@ (define_insn "*movv2sf_internal"
     #"
   [(set_attr "type" "mmx,mmxmov,mmxmov,ssecvt,ssecvt,sselog1,ssemov,ssemov,ssemov,*,*")
    (set_attr "unit" "*,*,*,mmx,mmx,*,*,*,*,*,*")
+   (set_attr "prefix_rep" "*,*,*,1,1,*,*,*,*,*,*")
    (set_attr "mode" "DI,DI,DI,DI,DI,V4SF,V4SF,V2SF,V2SF,DI,DI")])
 
 ;; %%% This multiword shite has got to go.
@@ -313,6 +327,7 @@ (define_insn "*mmx_addv2sf3"
   "TARGET_3DNOW && ix86_binary_operator_ok (PLUS, V2SFmode, operands)"
   "pfadd\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmxadd")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_expand "mmx_subv2sf3"
@@ -338,6 +353,7 @@ (define_insn "*mmx_subv2sf3"
    pfsub\t{%2, %0|%0, %2}
    pfsubr\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmxadd")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_expand "mmx_mulv2sf3"
@@ -354,6 +370,7 @@ (define_insn "*mmx_mulv2sf3"
   "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V2SFmode, operands)"
   "pfmul\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmxmul")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 ;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
@@ -381,6 +398,7 @@ (define_insn "*mmx_<code>v2sf3_finite"
    && ix86_binary_operator_ok (<CODE>, V2SFmode, operands)"
   "pf<maxminfprefix>\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmxadd")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_insn "*mmx_<code>v2sf3"
@@ -391,6 +409,7 @@ (define_insn "*mmx_<code>v2sf3"
   "TARGET_3DNOW"
   "pf<maxminfprefix>\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmxadd")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_insn "mmx_rcpv2sf2"
@@ -400,6 +419,7 @@ (define_insn "mmx_rcpv2sf2"
   "TARGET_3DNOW"
   "pfrcp\t{%1, %0|%0, %1}"
   [(set_attr "type" "mmx")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_insn "mmx_rcpit1v2sf3"
@@ -410,6 +430,7 @@ (define_insn "mmx_rcpit1v2sf3"
   "TARGET_3DNOW"
   "pfrcpit1\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmx")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_insn "mmx_rcpit2v2sf3"
@@ -420,6 +441,7 @@ (define_insn "mmx_rcpit2v2sf3"
   "TARGET_3DNOW"
   "pfrcpit2\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmx")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_insn "mmx_rsqrtv2sf2"
@@ -429,6 +451,7 @@ (define_insn "mmx_rsqrtv2sf2"
   "TARGET_3DNOW"
   "pfrsqrt\t{%1, %0|%0, %1}"
   [(set_attr "type" "mmx")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_insn "mmx_rsqit1v2sf3"
@@ -439,6 +462,7 @@ (define_insn "mmx_rsqit1v2sf3"
   "TARGET_3DNOW"
   "pfrsqit1\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmx")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_insn "mmx_haddv2sf3"
@@ -457,6 +481,7 @@ (define_insn "mmx_haddv2sf3"
   "TARGET_3DNOW"
   "pfacc\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmxadd")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_insn "mmx_hsubv2sf3"
@@ -475,6 +500,7 @@ (define_insn "mmx_hsubv2sf3"
   "TARGET_3DNOW_A"
   "pfnacc\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmxadd")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_insn "mmx_addsubv2sf3"
@@ -488,6 +514,7 @@ (define_insn "mmx_addsubv2sf3"
   "TARGET_3DNOW_A"
   "pfpnacc\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmxadd")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -510,6 +537,7 @@ (define_insn "*mmx_eqv2sf3"
   "TARGET_3DNOW && ix86_binary_operator_ok (EQ, V2SFmode, operands)"
   "pfcmpeq\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmxcmp")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_insn "mmx_gtv2sf3"
@@ -519,6 +547,7 @@ (define_insn "mmx_gtv2sf3"
   "TARGET_3DNOW"
   "pfcmpgt\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmxcmp")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_insn "mmx_gev2sf3"
@@ -528,6 +557,7 @@ (define_insn "mmx_gev2sf3"
   "TARGET_3DNOW"
   "pfcmpge\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmxcmp")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -542,6 +572,7 @@ (define_insn "mmx_pf2id"
   "TARGET_3DNOW"
   "pf2id\t{%1, %0|%0, %1}"
   [(set_attr "type" "mmxcvt")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_insn "mmx_pf2iw"
@@ -553,6 +584,7 @@ (define_insn "mmx_pf2iw"
   "TARGET_3DNOW_A"
   "pf2iw\t{%1, %0|%0, %1}"
   [(set_attr "type" "mmxcvt")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_insn "mmx_pi2fw"
@@ -564,6 +596,7 @@ (define_insn "mmx_pi2fw"
   "TARGET_3DNOW_A"
   "pi2fw\t{%1, %0|%0, %1}"
   [(set_attr "type" "mmxcvt")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_insn "mmx_floatv2si2"
@@ -572,6 +605,7 @@ (define_insn "mmx_floatv2si2"
   "TARGET_3DNOW"
   "pi2fd\t{%1, %0|%0, %1}"
   [(set_attr "type" "mmxcvt")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -587,6 +621,7 @@ (define_insn "mmx_pswapdv2sf2"
   "TARGET_3DNOW_A"
   "pswapd\t{%1, %0|%0, %1}"
   [(set_attr "type" "mmxcvt")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "V2SF")])
 
 (define_insn "*vec_dupv2sf"
@@ -887,6 +922,7 @@ (define_insn "*mmx_pmulhrwv4hi3"
   "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V4HImode, operands)"
   "pmulhrw\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmxmul")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "DI")])
 
 (define_expand "sse2_umulv1siv1di3"
@@ -965,6 +1001,10 @@ (define_insn "mmx_ashr<mode>3"
   "TARGET_MMX"
   "psra<mmxvecsize>\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmxshft")
+   (set (attr "length_immediate")
+     (if_then_else (match_operand 2 "const_int_operand" "")
+       (const_string "1")
+       (const_string "0")))
    (set_attr "mode" "DI")])
 
 (define_insn "mmx_lshr<mode>3"
@@ -975,6 +1015,10 @@ (define_insn "mmx_lshr<mode>3"
   "TARGET_MMX"
   "psrl<mmxvecsize>\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmxshft")
+   (set (attr "length_immediate")
+     (if_then_else (match_operand 2 "const_int_operand" "")
+       (const_string "1")
+       (const_string "0")))
    (set_attr "mode" "DI")])
 
 (define_insn "mmx_ashl<mode>3"
@@ -985,6 +1029,10 @@ (define_insn "mmx_ashl<mode>3"
   "TARGET_MMX"
   "psll<mmxvecsize>\t{%2, %0|%0, %2}"
   [(set_attr "type" "mmxshft")
+   (set (attr "length_immediate")
+     (if_then_else (match_operand 2 "const_int_operand" "")
+       (const_string "1")
+       (const_string "0")))
    (set_attr "mode" "DI")])
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -1205,6 +1253,7 @@ (define_insn "*mmx_pinsrw"
   return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
 }
   [(set_attr "type" "mmxcvt")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "DI")])
 
 (define_insn "mmx_pextrw"
@@ -1216,6 +1265,7 @@ (define_insn "mmx_pextrw"
   "TARGET_SSE || TARGET_3DNOW_A"
   "pextrw\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "mmxcvt")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "DI")])
 
 (define_expand "mmx_pshufw"
@@ -1253,6 +1303,7 @@ (define_insn "mmx_pshufw_1"
   return "pshufw\t{%2, %1, %0|%0, %1, %2}";
 }
   [(set_attr "type" "mmxcvt")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "DI")])
 
 (define_insn "mmx_pswapdv2si2"
@@ -1263,6 +1314,7 @@ (define_insn "mmx_pswapdv2si2"
   "TARGET_3DNOW_A"
   "pswapd\t{%1, %0|%0, %1}"
   [(set_attr "type" "mmxcvt")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "DI")])
 
 (define_insn "*vec_dupv4hi"
@@ -1273,6 +1325,7 @@ (define_insn "*vec_dupv4hi"
   "TARGET_SSE || TARGET_3DNOW_A"
   "pshufw\t{$0, %0, %0|%0, %0, 0}"
   [(set_attr "type" "mmxcvt")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "DI")])
 
 (define_insn "*vec_dupv2si"
@@ -1345,6 +1398,7 @@ (define_insn "*vec_extractv2si_1"
    #
    #"
   [(set_attr "type" "mmxcvt,sselog1,sselog1,sselog1,mmxmov,ssemov,imov")
+   (set_attr "length_immediate" "*,*,1,*,*,*,*")
    (set_attr "mode" "DI,TI,TI,V4SF,SI,SI,SI")])
 
 (define_split
@@ -1492,6 +1546,11 @@ (define_insn "*mmx_uavgv8qi3"
     return "pavgusb\t{%2, %0|%0, %2}";
 }
   [(set_attr "type" "mmxshft")
+   (set (attr "prefix_extra")
+     (if_then_else
+       (eq (symbol_ref "(TARGET_SSE || TARGET_3DNOW_A)") (const_int 0))
+       (const_string "1")
+       (const_string "*")))
    (set_attr "mode" "DI")])
 
 (define_expand "mmx_uavgv4hi3"
@@ -1602,6 +1661,7 @@ (define_insn "mmx_emms"
   "TARGET_MMX"
   "emms"
   [(set_attr "type" "mmx")
+   (set_attr "modrm" "0")
    (set_attr "memory" "unknown")])
 
 (define_insn "mmx_femms"
@@ -1625,4 +1685,5 @@ (define_insn "mmx_femms"
   "TARGET_3DNOW"
   "femms"
   [(set_attr "type" "mmx")
+   (set_attr "modrm" "0")
    (set_attr "memory" "none")])
--- gcc/config/i386/predicates.md.jj	2009-05-25 08:30:27.000000000 +0200
+++ gcc/config/i386/predicates.md	2009-05-25 10:19:38.000000000 +0200
@@ -84,6 +84,12 @@ (define_predicate "ext_QIreg_operand"
 		    && GET_MODE (op) == QImode
 		    && REGNO (op) > BX_REG")))
 
+;; Similarly, but don't check mode of the operand.
+(define_predicate "ext_QIreg_nomode_operand"
+  (and (match_code "reg")
+       (match_test "TARGET_64BIT
+		    && REGNO (op) > BX_REG")))
+
 ;; Return true if op is not xmm0 register.
 (define_predicate "reg_not_xmm0_operand"
    (and (match_operand 0 "register_operand")
@@ -587,11 +593,6 @@ (define_predicate "const128_operand"
   (and (match_code "const_int")
        (match_test "INTVAL (op) == 128")))
 
-;; Match exactly -128.
-(define_predicate "constm128_operand"
-  (and (match_code "const_int")
-       (match_test "INTVAL (op) == -128")))
-
 ;; Match 2, 4, or 8.  Used for leal multiplicands.
 (define_predicate "const248_operand"
   (match_code "const_int")
--- gcc/config/i386/i386.c.jj	2009-05-25 08:30:34.000000000 +0200
+++ gcc/config/i386/i386.c	2009-05-28 11:16:28.000000000 +0200
@@ -19349,9 +19349,33 @@ memory_address_length (rtx addr)
 	len = 1;
     }
 
-  /* Direct Addressing.  */
+  /* Direct Addressing.  In 64-bit mode mod 00 r/m 5
+     is not disp32, but disp32(%rip), so for disp32
+     SIB byte is needed, unless print_operand_address
+     optimizes it into disp32(%rip) or (%rip) is implied
+     by UNSPEC.  */
   else if (disp && !base && !index)
-    len = 4;
+    {
+      len = 4;
+      if (TARGET_64BIT)
+	{
+	  rtx symbol = disp;
+
+	  if (GET_CODE (disp) == CONST)
+	    symbol = XEXP (disp, 0);
+	  if (GET_CODE (symbol) == PLUS
+	      && CONST_INT_P (XEXP (symbol, 1)))
+	    symbol = XEXP (symbol, 0);
+
+	  if (GET_CODE (symbol) != LABEL_REF
+	      && (GET_CODE (symbol) != SYMBOL_REF
+		  || SYMBOL_REF_TLS_MODEL (symbol) != 0)
+	      && (GET_CODE (symbol) != UNSPEC
+		  || (XINT (symbol, 1) != UNSPEC_GOTPCREL
+		      && XINT (symbol, 1) != UNSPEC_GOTNTPOFF)))
+	    len += 1;
+	}
+    }
 
   else
     {
@@ -19366,7 +19390,7 @@ memory_address_length (rtx addr)
       /* ebp always wants a displacement.  Similarly r13.  */
       else if (REG_P (base)
 	       && (REGNO (base) == BP_REG || REGNO (base) == R13_REG))
-        len = 1;
+	len = 1;
 
       /* An index requires the two-byte modrm form....  */
       if (index
@@ -19378,6 +19402,16 @@ memory_address_length (rtx addr)
 	len += 1;
     }
 
+  switch (parts.seg)
+    {
+    case SEG_FS:
+    case SEG_GS:
+      len += 1;
+      break;
+    default:
+      break;
+    }
+
   return len;
 }
 
@@ -19392,30 +19426,50 @@ ix86_attr_length_immediate_default (rtx 
   for (i = recog_data.n_operands - 1; i >= 0; --i)
     if (CONSTANT_P (recog_data.operand[i]))
       {
+        enum attr_mode mode = get_attr_mode (insn);
+
 	gcc_assert (!len);
-	if (shortform && satisfies_constraint_K (recog_data.operand[i]))
-	  len = 1;
-	else
+	if (shortform && CONST_INT_P (recog_data.operand[i]))
 	  {
-	    switch (get_attr_mode (insn))
+	    HOST_WIDE_INT ival = INTVAL (recog_data.operand[i]);
+	    switch (mode)
 	      {
-		case MODE_QI:
-		  len+=1;
-		  break;
-		case MODE_HI:
-		  len+=2;
-		  break;
-		case MODE_SI:
-		  len+=4;
-		  break;
-		/* Immediates for DImode instructions are encoded as 32bit sign extended values.  */
-		case MODE_DI:
-		  len+=4;
-		  break;
-		default:
-		  fatal_insn ("unknown insn mode", insn);
+	      case MODE_QI:
+		len = 1;
+		continue;
+	      case MODE_HI:
+		ival = trunc_int_for_mode (ival, HImode);
+		break;
+	      case MODE_SI:
+		ival = trunc_int_for_mode (ival, SImode);
+		break;
+	      default:
+		break;
+	      }
+	    if (IN_RANGE (ival, -128, 127))
+	      {
+		len = 1;
+		continue;
 	      }
 	  }
+	switch (mode)
+	  {
+	  case MODE_QI:
+	    len = 1;
+	    break;
+	  case MODE_HI:
+	    len = 2;
+	    break;
+	  case MODE_SI:
+	    len = 4;
+	    break;
+	  /* Immediates for DImode instructions are encoded as 32bit sign extended values.  */
+	  case MODE_DI:
+	    len = 4;
+	    break;
+	  default:
+	    fatal_insn ("unknown insn mode", insn);
+	}
       }
   return len;
 }
@@ -19450,8 +19504,22 @@ ix86_attr_length_address_default (rtx in
   for (i = recog_data.n_operands - 1; i >= 0; --i)
     if (MEM_P (recog_data.operand[i]))
       {
+        constrain_operands_cached (reload_completed);
+        if (which_alternative != -1)
+	  {
+	    const char *constraints = recog_data.constraints[i];
+	    int alt = which_alternative;
+
+	    while (*constraints == '=' || *constraints == '+')
+	      constraints++;
+	    while (alt-- > 0)
+	      while (*constraints++ != ',')
+		;
+	    /* Skip ignored operands.  */
+	    if (*constraints == 'X')
+	      continue;
+	  }
 	return memory_address_length (XEXP (recog_data.operand[i], 0));
-	break;
       }
   return 0;
 }
@@ -19480,7 +19548,8 @@ ix86_attr_length_vex_default (rtx insn, 
     if (REG_P (recog_data.operand[i]))
       {
 	/* REX.W bit uses 3 byte VEX prefix.  */
-	if (GET_MODE (recog_data.operand[i]) == DImode)
+	if (GET_MODE (recog_data.operand[i]) == DImode
+	    && GENERAL_REG_P (recog_data.operand[i]))
 	  return 3 + 1;
       }
     else
--- gcc/config/i386/sse.md.jj	2009-05-21 16:02:22.000000000 +0200
+++ gcc/config/i386/sse.md	2009-05-28 09:24:40.000000000 +0200
@@ -437,6 +437,7 @@ (define_insn "sse2_movntsi"
   "TARGET_SSE2"
   "movnti\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssemov")
+   (set_attr "prefix_data16" "0")
    (set_attr "mode" "V2DF")])
 
 (define_insn "avx_lddqu<avxmodesuffix>"
@@ -459,6 +460,7 @@ (define_insn "sse3_lddqu"
   "lddqu\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssemov")
    (set_attr "movu" "1")
+   (set_attr "prefix_data16" "0")
    (set_attr "prefix_rep" "1")
    (set_attr "mode" "TI")])
 
@@ -1407,6 +1409,7 @@ (define_insn "avx_cmpp<avxmodesuffixf2c>
   "TARGET_AVX"
   "vcmpp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssecmp")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<MODE>")])
 
@@ -1423,6 +1426,7 @@ (define_insn "avx_cmps<ssemodesuffixf2c>
   "TARGET_AVX"
   "vcmps<ssemodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssecmp")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<ssescalarmode>")])
 
@@ -1437,6 +1441,7 @@ (define_insn "*avx_maskcmp<mode>3"
   "vcmp%D3p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ssecmp")
    (set_attr "prefix" "vex")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "<avxvecmode>")])
 
 (define_insn "<sse>_maskcmp<mode>3"
@@ -1448,6 +1453,7 @@ (define_insn "<sse>_maskcmp<mode>3"
    && !TARGET_SSE5"
   "cmp%D3<ssemodesuffixf4>\t{%2, %0|%0, %2}"
   [(set_attr "type" "ssecmp")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "<sse>_vmmaskcmp<mode>3"
@@ -1461,6 +1467,7 @@ (define_insn "<sse>_vmmaskcmp<mode>3"
   "SSE_VEC_FLOAT_MODE_P (<MODE>mode) && !TARGET_SSE5"
   "cmp%D3s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
   [(set_attr "type" "ssecmp")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "<ssescalarmode>")])
 
 (define_insn "<sse>_comi"
@@ -1476,6 +1483,11 @@ (define_insn "<sse>_comi"
   "%vcomis<ssemodefsuffix>\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecomi")
    (set_attr "prefix" "maybe_vex")
+   (set_attr "prefix_rep" "0")
+   (set (attr "prefix_data16")
+	(if_then_else (eq_attr "mode" "DF")
+		      (const_string "1")
+		      (const_string "0")))
    (set_attr "mode" "<MODE>")])
 
 (define_insn "<sse>_ucomi"
@@ -1491,6 +1503,11 @@ (define_insn "<sse>_ucomi"
   "%vucomis<ssemodefsuffix>\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecomi")
    (set_attr "prefix" "maybe_vex")
+   (set_attr "prefix_rep" "0")
+   (set (attr "prefix_data16")
+	(if_then_else (eq_attr "mode" "DF")
+		      (const_string "1")
+		      (const_string "0")))
    (set_attr "mode" "<MODE>")])
 
 (define_expand "vcond<mode>"
@@ -2222,6 +2239,7 @@ (define_insn "sse_cvttps2pi"
   "cvttps2pi\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt")
    (set_attr "unit" "mmx")
+   (set_attr "prefix_rep" "0")
    (set_attr "mode" "SF")])
 
 (define_insn "*avx_cvtsi2ss"
@@ -2261,6 +2279,7 @@ (define_insn "*avx_cvtsi2ssq"
   "TARGET_AVX && TARGET_64BIT"
   "vcvtsi2ssq\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseicvt")
+   (set_attr "length_vex" "4")
    (set_attr "prefix" "vex")
    (set_attr "mode" "SF")])
 
@@ -2274,6 +2293,7 @@ (define_insn "sse_cvtsi2ssq"
   "TARGET_SSE && TARGET_64BIT"
   "cvtsi2ssq\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseicvt")
+   (set_attr "prefix_rex" "1")
    (set_attr "athlon_decode" "vector,double")
    (set_attr "amdfam10_decode" "vector,double")
    (set_attr "mode" "SF")])
@@ -2420,6 +2440,7 @@ (define_insn "sse2_cvttps2dq"
   "cvttps2dq\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix_rep" "1")
+   (set_attr "prefix_data16" "0")
    (set_attr "mode" "TI")])
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -2435,6 +2456,7 @@ (define_insn "sse2_cvtpi2pd"
   "cvtpi2pd\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt")
    (set_attr "unit" "mmx,*")
+   (set_attr "prefix_data16" "1,*")
    (set_attr "mode" "V2DF")])
 
 (define_insn "sse2_cvtpd2pi"
@@ -2495,6 +2517,7 @@ (define_insn "*avx_cvtsi2sdq"
   "TARGET_AVX && TARGET_64BIT"
   "vcvtsi2sdq\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseicvt")
+   (set_attr "length_vex" "4")
    (set_attr "prefix" "vex")
    (set_attr "mode" "DF")])
 
@@ -2508,6 +2531,7 @@ (define_insn "sse2_cvtsi2sdq"
   "TARGET_SSE2 && TARGET_64BIT"
   "cvtsi2sdq\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseicvt")
+   (set_attr "prefix_rex" "1")
    (set_attr "mode" "DF")
    (set_attr "athlon_decode" "double,direct")
    (set_attr "amdfam10_decode" "vector,double")])
@@ -2649,6 +2673,7 @@ (define_insn "*sse2_cvtpd2dq"
 		       : \"cvtpd2dq\t{%1, %0|%0, %1}\";"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix_rep" "1")
+   (set_attr "prefix_data16" "0")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")
    (set_attr "amdfam10_decode" "double")])
@@ -2679,7 +2704,6 @@ (define_insn "*sse2_cvttpd2dq"
   "* return TARGET_AVX ? \"vcvttpd2dq{x}\t{%1, %0|%0, %1}\"
 		       : \"cvttpd2dq\t{%1, %0|%0, %1}\";"
   [(set_attr "type" "ssecvt")
-   (set_attr "prefix_rep" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")
    (set_attr "amdfam10_decode" "double")])
@@ -2798,6 +2822,7 @@ (define_insn "sse2_cvtps2pd"
   [(set_attr "type" "ssecvt")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "V2DF")
+   (set_attr "prefix_data16" "0")
    (set_attr "amdfam10_decode" "direct")])
 
 (define_expand "vec_unpacks_hi_v4sf"
@@ -3268,6 +3293,7 @@ (define_insn "avx_shufps256_1"
   return "vshufps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
 }
   [(set_attr "type" "sselog")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
 
@@ -3309,6 +3335,7 @@ (define_insn "*avx_shufps_<mode>"
   return "vshufps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
 }
   [(set_attr "type" "sselog")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V4SF")])
 
@@ -3334,6 +3361,7 @@ (define_insn "sse_shufps_<mode>"
   return "shufps\t{%3, %2, %0|%0, %2, %3}";
 }
   [(set_attr "type" "sselog")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "V4SF")])
 
 (define_insn "sse_storehps"
@@ -3441,6 +3469,7 @@ (define_insn "*avx_loadlps"
    vmovlps\t{%2, %1, %0|%0, %1, %2}
    vmovlps\t{%2, %0|%0, %2}"
   [(set_attr "type" "sselog,ssemov,ssemov")
+   (set_attr "length_immediate" "1,*,*")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V4SF,V2SF,V2SF")])
 
@@ -3457,6 +3486,7 @@ (define_insn "sse_loadlps"
    movlps\t{%2, %0|%0, %2}
    movlps\t{%2, %0|%0, %2}"
   [(set_attr "type" "sselog,ssemov,ssemov")
+   (set_attr "length_immediate" "1,*,*")
    (set_attr "mode" "V4SF,V2SF,V2SF")])
 
 (define_insn "*avx_movss"
@@ -3489,6 +3519,7 @@ (define_insn "*vec_dupv4sf_avx"
   "TARGET_AVX"
   "vshufps\t{$0, %1, %1, %0|%0, %1, %1, 0}"
   [(set_attr "type" "sselog1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V4SF")])
 
@@ -3499,6 +3530,7 @@ (define_insn "*vec_dupv4sf"
   "TARGET_SSE"
   "shufps\t{$0, %0, %0|%0, %0, 0}"
   [(set_attr "type" "sselog1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "V4SF")])
 
 (define_insn "*vec_concatv2sf_avx"
@@ -3514,6 +3546,8 @@ (define_insn "*vec_concatv2sf_avx"
    punpckldq\t{%2, %0|%0, %2}
    movd\t{%1, %0|%0, %1}"
   [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
+   (set_attr "length_immediate" "*,1,*,*,*")
+   (set_attr "prefix_extra" "*,1,*,*,*")
    (set (attr "prefix")
      (if_then_else (eq_attr "alternative" "3,4")
        (const_string "orig")
@@ -3535,7 +3569,9 @@ (define_insn "*vec_concatv2sf_sse4_1"
    punpckldq\t{%2, %0|%0, %2}
    movd\t{%1, %0|%0, %1}"
   [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
+   (set_attr "prefix_data16" "*,1,*,*,*")
    (set_attr "prefix_extra" "*,1,*,*,*")
+   (set_attr "length_immediate" "*,1,*,*,*")
    (set_attr "mode" "V4SF,V4SF,SF,DI,DI")])
 
 ;; ??? In theory we can match memory for the MMX alternative, but allowing
@@ -3636,6 +3672,8 @@ (define_insn "*vec_setv4sf_avx"
   return "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
 }
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V4SF")])
 
@@ -3652,7 +3690,9 @@ (define_insn "*vec_setv4sf_sse4_1"
   return "insertps\t{%3, %2, %0|%0, %2, %3}";
 }
   [(set_attr "type" "sselog")
+   (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "V4SF")])
 
 (define_insn "*avx_insertps"
@@ -3665,6 +3705,8 @@ (define_insn "*avx_insertps"
   "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
   [(set_attr "type" "sselog")
    (set_attr "prefix" "vex")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "V4SF")])
 
 (define_insn "sse4_1_insertps"
@@ -3676,7 +3718,9 @@ (define_insn "sse4_1_insertps"
   "TARGET_SSE4_1"
   "insertps\t{%3, %2, %0|%0, %2, %3}";
   [(set_attr "type" "sselog")
+   (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "V4SF")])
 
 (define_split
@@ -3751,6 +3795,8 @@ (define_insn "vec_extract_lo_<mode>"
   "TARGET_AVX"
   "vextractf128\t{$0x0, %1, %0|%0, %1, 0x0}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "memory" "none,store")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
@@ -3763,6 +3809,8 @@ (define_insn "vec_extract_hi_<mode>"
   "TARGET_AVX"
   "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "memory" "none,store")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
@@ -3776,6 +3824,8 @@ (define_insn "vec_extract_lo_<mode>"
   "TARGET_AVX"
   "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "memory" "none,store")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
@@ -3789,6 +3839,8 @@ (define_insn "vec_extract_hi_<mode>"
   "TARGET_AVX"
   "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "memory" "none,store")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
@@ -3804,6 +3856,8 @@ (define_insn "vec_extract_lo_v16hi"
   "TARGET_AVX"
   "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "memory" "none,store")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
@@ -3819,6 +3873,8 @@ (define_insn "vec_extract_hi_v16hi"
   "TARGET_AVX"
   "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "memory" "none,store")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
@@ -3838,6 +3894,8 @@ (define_insn "vec_extract_lo_v32qi"
   "TARGET_AVX"
   "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "memory" "none,store")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
@@ -3857,6 +3915,8 @@ (define_insn "vec_extract_hi_v32qi"
   "TARGET_AVX"
   "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "memory" "none,store")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
@@ -3869,7 +3929,9 @@ (define_insn "*sse4_1_extractps"
   "TARGET_SSE4_1"
   "%vextractps\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "V4SF")])
 
@@ -3962,6 +4024,7 @@ (define_insn "sse2_unpckhpd"
    movlpd\t{%H1, %0|%0, %H1}
    movhpd\t{%1, %0|%0, %1}"
   [(set_attr "type" "sselog,ssemov,ssemov")
+   (set_attr "prefix_data16" "*,1,1")
    (set_attr "mode" "V2DF,V1DF,V1DF")])
 
 (define_insn "avx_movddup256"
@@ -4082,6 +4145,7 @@ (define_insn "sse2_unpcklpd"
    movhpd\t{%2, %0|%0, %2}
    movlpd\t{%2, %H0|%H0, %2}"
   [(set_attr "type" "sselog,ssemov,ssemov")
+   (set_attr "prefix_data16" "*,1,1")
    (set_attr "mode" "V2DF,V1DF,V1DF")])
 
 (define_expand "avx_shufpd256"
@@ -4122,6 +4186,7 @@ (define_insn "avx_shufpd256_1"
   return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
 }
   [(set_attr "type" "sselog")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V4DF")])
 
@@ -4258,6 +4323,7 @@ (define_insn "*avx_shufpd_<mode>"
   return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
 }
   [(set_attr "type" "sselog")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V2DF")])
 
@@ -4279,6 +4345,7 @@ (define_insn "sse2_shufpd_<mode>"
   return "shufpd\t{%3, %2, %0|%0, %2, %3}";
 }
   [(set_attr "type" "sselog")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "V2DF")])
 
 ;; Avoid combining registers from different units in a single alternative,
@@ -4312,6 +4379,7 @@ (define_insn "sse2_storehpd"
    #
    #"
   [(set_attr "type" "ssemov,sselog1,ssemov,fmov,imov")
+   (set_attr "prefix_data16" "1,*,*,*,*")
    (set_attr "mode" "V1DF,V2DF,DF,DF,DF")])
 
 (define_split
@@ -4340,6 +4408,7 @@ (define_insn "sse2_storelpd"
    #
    #"
   [(set_attr "type" "ssemov,ssemov,ssemov,fmov,imov")
+   (set_attr "prefix_data16" "1,*,*,*,*")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "V1DF,DF,DF,DF,DF")])
 
@@ -4406,6 +4475,8 @@ (define_insn "sse2_loadhpd"
    #
    #"
   [(set_attr "type" "ssemov,sselog,sselog,ssemov,fmov,imov")
+   (set_attr "prefix_data16" "1,*,*,*,*,*")
+   (set_attr "length_immediate" "*,*,1,*,*,*")
    (set_attr "mode" "V1DF,V2DF,V2DF,DF,DF,DF")])
 
 (define_split
@@ -4469,6 +4540,8 @@ (define_insn "sse2_loadlpd"
    #
    #"
   [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov,fmov,imov")
+   (set_attr "prefix_data16" "*,1,*,*,1,*,*,*")
+   (set_attr "length_immediate" "*,*,*,1,*,*,*,*")
    (set_attr "mode" "DF,V1DF,V1DF,V2DF,V1DF,DF,DF,DF")])
 
 (define_split
@@ -4544,6 +4617,8 @@ (define_insn "sse2_movsd"
    movhps\t{%H1, %0|%0, %H1}
    movhps\t{%1, %H0|%H0, %1}"
   [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
+   (set_attr "prefix_data16" "*,1,1,*,*,*")
+   (set_attr "length_immediate" "*,*,*,1,*,*")
    (set_attr "mode" "DF,V1DF,V1DF,V2DF,V1DF,V1DF")])
 
 (define_insn "*vec_dupv2df_sse3"
@@ -4603,6 +4678,7 @@ (define_insn "*vec_concatv2df"
    movlhps\t{%2, %0|%0, %2}
    movhps\t{%2, %0|%0, %2}"
   [(set_attr "type" "sselog,ssemov,ssemov,ssemov,ssemov")
+   (set_attr "prefix_data16" "*,1,*,*,*")
    (set_attr "mode" "V2DF,V1DF,DF,V4SF,V2SF")])
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -4951,6 +5027,7 @@ (define_insn "*avx_mulv2siv2di3"
   "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
   "vpmuldq\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseimul")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -5097,6 +5174,7 @@ (define_insn "*avx_mulv4si3"
   "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
   "vpmulld\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseimul")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -5492,6 +5570,10 @@ (define_insn "*avx_ashr<mode>3"
   "vpsra<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseishft")
    (set_attr "prefix" "vex")
+   (set (attr "length_immediate")
+     (if_then_else (match_operand 2 "const_int_operand" "")
+       (const_string "1")
+       (const_string "0")))
    (set_attr "mode" "TI")])
 
 (define_insn "ashr<mode>3"
@@ -5503,6 +5585,10 @@ (define_insn "ashr<mode>3"
   "psra<ssevecsize>\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseishft")
    (set_attr "prefix_data16" "1")
+   (set (attr "length_immediate")
+     (if_then_else (match_operand 2 "const_int_operand" "")
+       (const_string "1")
+       (const_string "0")))
    (set_attr "mode" "TI")])
 
 (define_insn "*avx_lshr<mode>3"
@@ -5514,6 +5600,10 @@ (define_insn "*avx_lshr<mode>3"
   "vpsrl<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseishft")
    (set_attr "prefix" "vex")
+   (set (attr "length_immediate")
+     (if_then_else (match_operand 2 "const_int_operand" "")
+       (const_string "1")
+       (const_string "0")))
    (set_attr "mode" "TI")])
 
 (define_insn "lshr<mode>3"
@@ -5525,6 +5615,10 @@ (define_insn "lshr<mode>3"
   "psrl<ssevecsize>\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseishft")
    (set_attr "prefix_data16" "1")
+   (set (attr "length_immediate")
+     (if_then_else (match_operand 2 "const_int_operand" "")
+       (const_string "1")
+       (const_string "0")))
    (set_attr "mode" "TI")])
 
 (define_insn "*avx_ashl<mode>3"
@@ -5536,6 +5630,10 @@ (define_insn "*avx_ashl<mode>3"
   "vpsll<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseishft")
    (set_attr "prefix" "vex")
+   (set (attr "length_immediate")
+     (if_then_else (match_operand 2 "const_int_operand" "")
+       (const_string "1")
+       (const_string "0")))
    (set_attr "mode" "TI")])
 
 (define_insn "ashl<mode>3"
@@ -5547,6 +5645,10 @@ (define_insn "ashl<mode>3"
   "psll<ssevecsize>\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseishft")
    (set_attr "prefix_data16" "1")
+   (set (attr "length_immediate")
+     (if_then_else (match_operand 2 "const_int_operand" "")
+       (const_string "1")
+       (const_string "0")))
    (set_attr "mode" "TI")])
 
 (define_expand "vec_shl_<mode>"
@@ -5577,6 +5679,12 @@ (define_insn "*avx_<code><mode>3"
   "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
   "vp<maxminiprefix><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseiadd")
+   (set (attr "prefix_extra")
+     (if_then_else
+       (ne (symbol_ref "<MODE>mode != ((<CODE> == SMAX || <CODE> == SMIN) ? V8HImode : V16QImode)")
+	   (const_int 0))
+       (const_string "1")
+       (const_string "0")))
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -5781,6 +5889,10 @@ (define_insn "*avx_eq<mode>3"
   "TARGET_AVX && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
   "vpcmpeq<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ssecmp")
+   (set (attr "prefix_extra")
+     (if_then_else (match_operand:V2DI 0 "" "")
+       (const_string "1")
+       (const_string "*")))
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -5823,6 +5935,10 @@ (define_insn "*avx_gt<mode>3"
   "TARGET_AVX"
   "vpcmpgt<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ssecmp")
+   (set (attr "prefix_extra")
+     (if_then_else (match_operand:V2DI 0 "" "")
+       (const_string "1")
+       (const_string "*")))
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -5845,6 +5961,7 @@ (define_insn "sse4_2_gtv2di3"
   "TARGET_SSE4_2"
   "pcmpgtq\t{%2, %0|%0, %2}"
   [(set_attr "type" "ssecmp")
+   (set_attr "prefix_extra" "1")
    (set_attr "mode" "TI")])
 
 (define_expand "vcond<mode>"
@@ -6603,6 +6720,11 @@ (define_insn "*avx_pinsr<ssevecsize>"
   return "vpinsr<ssevecsize>\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
 }
   [(set_attr "type" "sselog")
+   (set (attr "prefix_extra")
+     (if_then_else (match_operand:V8HI 0 "register_operand" "")
+       (const_string "0")
+       (const_string "1")))
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -6620,6 +6742,7 @@ (define_insn "*sse4_1_pinsrb"
 }
   [(set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_insn "*sse2_pinsrw"
@@ -6636,6 +6759,7 @@ (define_insn "*sse2_pinsrw"
 }
   [(set_attr "type" "sselog")
    (set_attr "prefix_data16" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 ;; It must come before sse2_loadld since it is preferred.
@@ -6653,6 +6777,7 @@ (define_insn "*sse4_1_pinsrd"
 }
   [(set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_insn "*avx_pinsrq"
@@ -6668,6 +6793,8 @@ (define_insn "*avx_pinsrq"
   return "vpinsrq\t{%3, %2, %1, %0|%0, %1, %2, %3}";
 }
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -6684,7 +6811,9 @@ (define_insn "*sse4_1_pinsrq"
   return "pinsrq\t{%3, %2, %0|%0, %2, %3}";
 }
   [(set_attr "type" "sselog")
+   (set_attr "prefix_rex" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_insn "*sse4_1_pextrb"
@@ -6697,6 +6826,7 @@ (define_insn "*sse4_1_pextrb"
   "%vpextrb\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")])
 
@@ -6709,6 +6839,7 @@ (define_insn "*sse4_1_pextrb_memory"
   "%vpextrb\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")])
 
@@ -6722,6 +6853,7 @@ (define_insn "*sse2_pextrw"
   "%vpextrw\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog")
    (set_attr "prefix_data16" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")])
 
@@ -6734,6 +6866,7 @@ (define_insn "*sse4_1_pextrw_memory"
   "%vpextrw\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")])
 
@@ -6746,6 +6879,7 @@ (define_insn "*sse4_1_pextrd"
   "%vpextrd\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")])
 
@@ -6758,7 +6892,9 @@ (define_insn "*sse4_1_pextrq"
   "TARGET_SSE4_1 && TARGET_64BIT"
   "%vpextrq\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_rex" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")])
 
@@ -6798,7 +6934,8 @@ (define_insn "sse2_pshufd_1"
 }
   [(set_attr "type" "sselog1")
    (set_attr "prefix_data16" "1")
-   (set_attr "prefix" "vex")
+   (set_attr "prefix" "maybe_vex")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_expand "sse2_pshuflw"
@@ -6840,8 +6977,10 @@ (define_insn "sse2_pshuflw_1"
   return "%vpshuflw\t{%2, %1, %0|%0, %1, %2}";
 }
   [(set_attr "type" "sselog")
+   (set_attr "prefix_data16" "0")
    (set_attr "prefix_rep" "1")
    (set_attr "prefix" "maybe_vex")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_expand "sse2_pshufhw"
@@ -6884,7 +7023,9 @@ (define_insn "sse2_pshufhw_1"
 }
   [(set_attr "type" "sselog")
    (set_attr "prefix_rep" "1")
+   (set_attr "prefix_data16" "0")
    (set_attr "prefix" "maybe_vex")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_expand "sse2_loadd"
@@ -7020,6 +7161,7 @@ (define_insn "*vec_extractv2di_1_rex64_a
    vmovq\t{%H1, %0|%0, %H1}
    vmov{q}\t{%H1, %0|%0, %H1}"
   [(set_attr "type" "ssemov,sseishft,ssemov,imov")
+   (set_attr "length_immediate" "*,1,*,*")
    (set_attr "memory" "*,none,*,*")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V2SF,TI,TI,DI")])
@@ -7036,6 +7178,7 @@ (define_insn "*vec_extractv2di_1_rex64"
    movq\t{%H1, %0|%0, %H1}
    mov{q}\t{%H1, %0|%0, %H1}"
   [(set_attr "type" "ssemov,sseishft,ssemov,imov")
+   (set_attr "length_immediate" "*,1,*,*")
    (set_attr "atom_unit" "*,sishuf,*,*")
    (set_attr "memory" "*,none,*,*")
    (set_attr "mode" "V2SF,TI,TI,DI")])
@@ -7053,6 +7196,7 @@ (define_insn "*vec_extractv2di_1_avx"
    vpsrldq\t{$8, %1, %0|%0, %1, 8}
    vmovq\t{%H1, %0|%0, %H1}"
   [(set_attr "type" "ssemov,sseishft,ssemov")
+   (set_attr "length_immediate" "*,1,*")
    (set_attr "memory" "*,none,*")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V2SF,TI,TI")])
@@ -7069,6 +7213,7 @@ (define_insn "*vec_extractv2di_1_sse2"
    psrldq\t{$8, %0|%0, 8}
    movq\t{%H1, %0|%0, %H1}"
   [(set_attr "type" "ssemov,sseishft,ssemov")
+   (set_attr "length_immediate" "*,1,*")
    (set_attr "atom_unit" "*,sishuf,*")
    (set_attr "memory" "*,none,*")
    (set_attr "mode" "V2SF,TI,TI")])
@@ -7098,6 +7243,7 @@ (define_insn "*vec_dupv4si"
    shufps\t{$0, %0, %0|%0, %0, 0}"
   [(set_attr "type" "sselog1")
    (set_attr "prefix" "maybe_vex,orig")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI,V4SF")])
 
 (define_insn "*vec_dupv2di_avx"
@@ -7134,6 +7280,8 @@ (define_insn "*vec_concatv2si_avx"
    punpckldq\t{%2, %0|%0, %2}
    movd\t{%1, %0|%0, %1}"
   [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
+   (set_attr "prefix_extra" "1,*,*,*,*")
+   (set_attr "length_immediate" "1,*,*,*,*")
    (set (attr "prefix")
      (if_then_else (eq_attr "alternative" "3,4")
        (const_string "orig")
@@ -7154,6 +7302,7 @@ (define_insn "*vec_concatv2si_sse4_1"
    movd\t{%1, %0|%0, %1}"
   [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
    (set_attr "prefix_extra" "1,*,*,*,*")
+   (set_attr "length_immediate" "1,*,*,*,*")
    (set_attr "mode" "TI,TI,TI,DI,DI")])
 
 ;; ??? In theory we can match memory for the MMX alternative, but allowing
@@ -7260,6 +7409,8 @@ (define_insn "*vec_concatv2di_rex64_avx"
    vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
    vmovhps\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,ssemov")
+   (set_attr "prefix_extra" "1,*,*,*,*,*")
+   (set_attr "length_immediate" "1,*,*,*,*,*")
    (set (attr "prefix")
      (if_then_else (eq_attr "alternative" "3")
        (const_string "orig")
@@ -7281,7 +7432,9 @@ (define_insn "*vec_concatv2di_rex64_sse4
    movlhps\t{%2, %0|%0, %2}
    movhps\t{%2, %0|%0, %2}"
   [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
+   (set_attr "prefix_rex" "1,*,1,*,*,*,*")
    (set_attr "prefix_extra" "1,*,*,*,*,*,*")
+   (set_attr "length_immediate" "1,*,*,*,*,*,*")
    (set_attr "mode" "TI,TI,TI,TI,TI,V4SF,V2SF")])
 
 (define_insn "*vec_concatv2di_rex64_sse"
@@ -7298,6 +7451,7 @@ (define_insn "*vec_concatv2di_rex64_sse"
    movlhps\t{%2, %0|%0, %2}
    movhps\t{%2, %0|%0, %2}"
   [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
+   (set_attr "prefix_rex" "*,1,*,*,*,*")
    (set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF")])
 
 (define_expand "vec_unpacku_hi_v16qi"
@@ -7684,6 +7838,8 @@ (define_insn "*sse2_maskmovdqu"
   "%vmaskmovdqu\t{%2, %1|%1, %2}"
   [(set_attr "type" "ssemov")
    (set_attr "prefix_data16" "1")
+   ;; The implicit %rdi operand confuses default length_vex computation.
+   (set_attr "length_vex" "3")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")])
 
@@ -7698,6 +7854,9 @@ (define_insn "*sse2_maskmovdqu_rex64"
   "%vmaskmovdqu\t{%2, %1|%1, %2}"
   [(set_attr "type" "ssemov")
    (set_attr "prefix_data16" "1")
+   ;; The implicit %rdi operand confuses default length_vex computation.
+   (set (attr "length_vex")
+     (symbol_ref ("REGNO (operands[2]) >= FIRST_REX_SSE_REG ? 3 + 1 : 2 + 1")))
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")])
 
@@ -7736,6 +7895,7 @@ (define_insn "*sse_sfence"
   "TARGET_SSE || TARGET_3DNOW_A"
   "sfence"
   [(set_attr "type" "sse")
+   (set_attr "length_address" "0")
    (set_attr "atom_sse_attr" "fence")
    (set_attr "memory" "unknown")])
 
@@ -7763,6 +7923,7 @@ (define_insn "*sse2_mfence"
   "TARGET_64BIT || TARGET_SSE2"
   "mfence"
   [(set_attr "type" "sse")
+   (set_attr "length_address" "0")
    (set_attr "atom_sse_attr" "fence")
    (set_attr "memory" "unknown")])
 
@@ -7781,6 +7942,7 @@ (define_insn "*sse2_lfence"
   "TARGET_SSE2"
   "lfence"
   [(set_attr "type" "sse")
+   (set_attr "length_address" "0")
    (set_attr "atom_sse_attr" "lfence")
    (set_attr "memory" "unknown")])
 
@@ -7862,6 +8024,7 @@ (define_insn "*avx_phaddwv8hi3"
   "TARGET_AVX"
   "vphaddw\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseiadd")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -7936,6 +8099,7 @@ (define_insn "ssse3_phaddwv4hi3"
   [(set_attr "type" "sseiadd")
    (set_attr "atom_unit" "complex")
    (set_attr "prefix_extra" "1")
+   (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
    (set_attr "mode" "DI")])
 
 (define_insn "*avx_phadddv4si3"
@@ -7962,6 +8126,7 @@ (define_insn "*avx_phadddv4si3"
   "TARGET_AVX"
   "vphaddd\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseiadd")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -8012,6 +8177,7 @@ (define_insn "ssse3_phadddv2si3"
   [(set_attr "type" "sseiadd")
    (set_attr "atom_unit" "complex")
    (set_attr "prefix_extra" "1")
+   (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
    (set_attr "mode" "DI")])
 
 (define_insn "*avx_phaddswv8hi3"
@@ -8054,6 +8220,7 @@ (define_insn "*avx_phaddswv8hi3"
   "TARGET_AVX"
   "vphaddsw\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseiadd")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -8128,6 +8295,7 @@ (define_insn "ssse3_phaddswv4hi3"
   [(set_attr "type" "sseiadd")
    (set_attr "atom_unit" "complex")
    (set_attr "prefix_extra" "1")
+   (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
    (set_attr "mode" "DI")])
 
 (define_insn "*avx_phsubwv8hi3"
@@ -8170,6 +8338,7 @@ (define_insn "*avx_phsubwv8hi3"
   "TARGET_AVX"
   "vphsubw\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseiadd")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -8244,6 +8413,7 @@ (define_insn "ssse3_phsubwv4hi3"
   [(set_attr "type" "sseiadd")
    (set_attr "atom_unit" "complex")
    (set_attr "prefix_extra" "1")
+   (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
    (set_attr "mode" "DI")])
 
 (define_insn "*avx_phsubdv4si3"
@@ -8270,6 +8440,7 @@ (define_insn "*avx_phsubdv4si3"
   "TARGET_AVX"
   "vphsubd\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseiadd")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -8320,6 +8491,7 @@ (define_insn "ssse3_phsubdv2si3"
   [(set_attr "type" "sseiadd")
    (set_attr "atom_unit" "complex")
    (set_attr "prefix_extra" "1")
+   (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
    (set_attr "mode" "DI")])
 
 (define_insn "*avx_phsubswv8hi3"
@@ -8362,6 +8534,7 @@ (define_insn "*avx_phsubswv8hi3"
   "TARGET_AVX"
   "vphsubsw\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseiadd")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -8436,6 +8609,7 @@ (define_insn "ssse3_phsubswv4hi3"
   [(set_attr "type" "sseiadd")
    (set_attr "atom_unit" "complex")
    (set_attr "prefix_extra" "1")
+   (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
    (set_attr "mode" "DI")])
 
 (define_insn "*avx_pmaddubsw128"
@@ -8488,6 +8662,7 @@ (define_insn "*avx_pmaddubsw128"
   "TARGET_AVX"
   "vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseiadd")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -8582,6 +8757,7 @@ (define_insn "ssse3_pmaddubsw"
   [(set_attr "type" "sseiadd")
    (set_attr "atom_unit" "simul")
    (set_attr "prefix_extra" "1")
+   (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
    (set_attr "mode" "DI")])
 
 (define_expand "ssse3_pmulhrswv8hi3"
@@ -8624,6 +8800,7 @@ (define_insn "*avx_pmulhrswv8hi3"
   "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
   "vpmulhrsw\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseimul")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -8688,6 +8865,7 @@ (define_insn "*ssse3_pmulhrswv4hi3"
   "pmulhrsw\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseimul")
    (set_attr "prefix_extra" "1")
+   (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
    (set_attr "mode" "DI")])
 
 (define_insn "*avx_pshufbv16qi3"
@@ -8698,6 +8876,7 @@ (define_insn "*avx_pshufbv16qi3"
   "TARGET_AVX"
   "vpshufb\t{%2, %1, %0|%0, %1, %2}";
   [(set_attr "type" "sselog1")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -8722,6 +8901,7 @@ (define_insn "ssse3_pshufbv8qi3"
   "pshufb\t{%2, %0|%0, %2}";
   [(set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
+   (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
    (set_attr "mode" "DI")])
 
 (define_insn "*avx_psign<mode>3"
@@ -8733,6 +8913,7 @@ (define_insn "*avx_psign<mode>3"
   "TARGET_AVX"
   "vpsign<ssevecsize>\t{%2, %1, %0|%0, %1, %2}";
   [(set_attr "type" "sselog1")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -8759,6 +8940,7 @@ (define_insn "ssse3_psign<mode>3"
   "psign<mmxvecsize>\t{%2, %0|%0, %2}";
   [(set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
+   (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
    (set_attr "mode" "DI")])
 
 (define_insn "*avx_palignrti"
@@ -8773,6 +8955,8 @@ (define_insn "*avx_palignrti"
   return "vpalignr\t{%3, %2, %1, %0|%0, %1, %2, %3}";
 }
   [(set_attr "type" "sseishft")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -8791,6 +8975,7 @@ (define_insn "ssse3_palignrti"
    (set_attr "atom_unit" "sishuf")
    (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_insn "ssse3_palignrdi"
@@ -8807,6 +8992,8 @@ (define_insn "ssse3_palignrdi"
   [(set_attr "type" "sseishft")
    (set_attr "atom_unit" "sishuf")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
+   (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
    (set_attr "mode" "DI")])
 
 (define_insn "abs<mode>2"
@@ -8826,7 +9013,9 @@ (define_insn "abs<mode>2"
   "TARGET_SSSE3"
   "pabs<mmxvecsize>\t{%1, %0|%0, %1}";
   [(set_attr "type" "sselog1")
+   (set_attr "prefix_rep" "0")
    (set_attr "prefix_extra" "1")
+   (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
    (set_attr "mode" "DI")])
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -8867,6 +9056,7 @@ (define_insn "sse4a_extrqi"
   "extrq\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "sse")
    (set_attr "prefix_data16" "1")
+   (set_attr "length_immediate" "2")
    (set_attr "mode" "TI")])
 
 (define_insn "sse4a_extrq"
@@ -8890,7 +9080,9 @@ (define_insn "sse4a_insertqi"
   "TARGET_SSE4A"
   "insertq\t{%4, %3, %2, %0|%0, %2, %3, %4}"
   [(set_attr "type" "sseins")
+   (set_attr "prefix_data16" "0")
    (set_attr "prefix_rep" "1")
+   (set_attr "length_immediate" "2")
    (set_attr "mode" "TI")])
 
 (define_insn "sse4a_insertq"
@@ -8901,6 +9093,7 @@ (define_insn "sse4a_insertq"
   "TARGET_SSE4A"
   "insertq\t{%2, %0|%0, %2}"
   [(set_attr "type" "sseins")
+   (set_attr "prefix_data16" "0")
    (set_attr "prefix_rep" "1")
    (set_attr "mode" "TI")])
 
@@ -8919,6 +9112,8 @@ (define_insn "avx_blendp<avxmodesuffixf2
   "TARGET_AVX"
   "vblendp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemov")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<avxvecmode>")])
 
@@ -8932,6 +9127,8 @@ (define_insn "avx_blendvp<avxmodesuffixf
   "TARGET_AVX"
   "vblendvp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemov")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<avxvecmode>")])
 
@@ -8944,7 +9141,9 @@ (define_insn "sse4_1_blendp<ssemodesuffi
   "TARGET_SSE4_1"
   "blendp<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "ssemov")
+   (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "sse4_1_blendvp<ssemodesuffixf2c>"
@@ -8957,6 +9156,7 @@ (define_insn "sse4_1_blendvp<ssemodesuff
   "TARGET_SSE4_1"
   "blendvp<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "ssemov")
+   (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
    (set_attr "mode" "<MODE>")])
 
@@ -8971,6 +9171,8 @@ (define_insn "avx_dpp<avxmodesuffixf2c><
   "vdpp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemul")
    (set_attr "prefix" "vex")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "<avxvecmode>")])
 
 (define_insn "sse4_1_dpp<ssemodesuffixf2c>"
@@ -8983,7 +9185,9 @@ (define_insn "sse4_1_dpp<ssemodesuffixf2
   "TARGET_SSE4_1"
   "dpp<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "ssemul")
+   (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "sse4_1_movntdqa"
@@ -9007,6 +9211,8 @@ (define_insn "*avx_mpsadbw"
   "vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "sselog1")
    (set_attr "prefix" "vex")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_insn "sse4_1_mpsadbw"
@@ -9019,6 +9225,7 @@ (define_insn "sse4_1_mpsadbw"
   "mpsadbw\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_insn "*avx_packusdw"
@@ -9031,6 +9238,7 @@ (define_insn "*avx_packusdw"
   "TARGET_AVX"
   "vpackusdw\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -9056,6 +9264,8 @@ (define_insn "*avx_pblendvb"
   "TARGET_AVX"
   "vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemov")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -9081,6 +9291,8 @@ (define_insn "*avx_pblendw"
   "vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemov")
    (set_attr "prefix" "vex")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_insn "sse4_1_pblendw"
@@ -9093,6 +9305,7 @@ (define_insn "sse4_1_pblendw"
   "pblendw\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_insn "sse4_1_phminposuw"
@@ -9504,6 +9717,7 @@ (define_insn "avx_vtestp<avxmodesuffixf2
   "TARGET_AVX"
   "vtestp<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecomi")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<MODE>")])
 
@@ -9517,6 +9731,7 @@ (define_insn "avx_ptest256"
   "TARGET_AVX"
   "vptest\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecomi")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "OI")])
 
@@ -9541,6 +9756,8 @@ (define_insn "avx_roundp<avxmodesuffixf2
   "TARGET_AVX"
   "vroundp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ssecvt")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<MODE>")])
 
@@ -9553,7 +9770,9 @@ (define_insn "sse4_1_roundp<ssemodesuffi
   "TARGET_ROUND"
   "%vroundp<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "ssecvt")
+   (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "<MODE>")])
 
@@ -9569,6 +9788,8 @@ (define_insn "*avx_rounds<ssemodesuffixf
   "TARGET_AVX"
   "vrounds<ssemodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssecvt")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<MODE>")])
 
@@ -9584,7 +9805,9 @@ (define_insn "sse4_1_rounds<ssemodesuffi
   "TARGET_ROUND"
   "rounds<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "ssecvt")
+   (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "<MODE>")])
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -9646,6 +9869,7 @@ (define_insn_and_split "sse4_2_pcmpestr"
   [(set_attr "type" "sselog")
    (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "memory" "none,load")
    (set_attr "mode" "TI")])
 
@@ -9672,6 +9896,7 @@ (define_insn "sse4_2_pcmpestri"
    (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "maybe_vex")
+   (set_attr "length_immediate" "1")
    (set_attr "memory" "none,load")
    (set_attr "mode" "TI")])
 
@@ -9697,6 +9922,7 @@ (define_insn "sse4_2_pcmpestrm"
   [(set_attr "type" "sselog")
    (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "memory" "none,load")
    (set_attr "mode" "TI")])
@@ -9721,6 +9947,7 @@ (define_insn "sse4_2_pcmpestr_cconly"
   [(set_attr "type" "sselog")
    (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "memory" "none,load,none,load")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")])
@@ -9769,6 +9996,7 @@ (define_insn_and_split "sse4_2_pcmpistr"
   [(set_attr "type" "sselog")
    (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "memory" "none,load")
    (set_attr "mode" "TI")])
 
@@ -9790,6 +10018,7 @@ (define_insn "sse4_2_pcmpistri"
   [(set_attr "type" "sselog")
    (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "memory" "none,load")
    (set_attr "mode" "TI")])
@@ -9812,6 +10041,7 @@ (define_insn "sse4_2_pcmpistrm"
   [(set_attr "type" "sselog")
    (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "memory" "none,load")
    (set_attr "mode" "TI")])
@@ -9834,6 +10064,7 @@ (define_insn "sse4_2_pcmpistr_cconly"
   [(set_attr "type" "sselog")
    (set_attr "prefix_data16" "1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "memory" "none,load,none,load")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")])
@@ -10832,6 +11063,8 @@ (define_insn "sse5_pperm_zero_v16qi_v8hi
        || register_operand (operands[2], V16QImode))"
   "pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
   [(set_attr "type" "sseadd")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_extra" "2")
    (set_attr "mode" "TI")])
 
 (define_insn "sse5_pperm_sign_v16qi_v8hi"
@@ -10846,6 +11079,8 @@ (define_insn "sse5_pperm_sign_v16qi_v8hi
        || register_operand (operands[2], V16QImode))"
   "pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
   [(set_attr "type" "sseadd")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_extra" "2")
    (set_attr "mode" "TI")])
 
 (define_insn "sse5_pperm_zero_v8hi_v4si"
@@ -10860,6 +11095,8 @@ (define_insn "sse5_pperm_zero_v8hi_v4si"
        || register_operand (operands[2], V16QImode))"
   "pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
   [(set_attr "type" "sseadd")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_extra" "2")
    (set_attr "mode" "TI")])
 
 (define_insn "sse5_pperm_sign_v8hi_v4si"
@@ -10874,6 +11111,8 @@ (define_insn "sse5_pperm_sign_v8hi_v4si"
        || register_operand (operands[2], V16QImode))"
   "pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
   [(set_attr "type" "sseadd")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_extra" "2")
    (set_attr "mode" "TI")])
 
 (define_insn "sse5_pperm_zero_v4si_v2di"
@@ -10888,6 +11127,8 @@ (define_insn "sse5_pperm_zero_v4si_v2di"
        || register_operand (operands[2], V16QImode))"
   "pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
   [(set_attr "type" "sseadd")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_extra" "2")
    (set_attr "mode" "TI")])
 
 (define_insn "sse5_pperm_sign_v4si_v2di"
@@ -10902,6 +11143,8 @@ (define_insn "sse5_pperm_sign_v4si_v2di"
        || register_operand (operands[2], V16QImode))"
   "pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
   [(set_attr "type" "sseadd")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_extra" "2")
    (set_attr "mode" "TI")])
 
 ;; SSE5 pack instructions that combine two vectors into a smaller vector
@@ -11030,6 +11273,7 @@ (define_insn "sse5_rotl<mode>3"
   "TARGET_SSE5"
   "prot<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseishft")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_insn "sse5_rotr<mode>3"
@@ -11043,6 +11287,7 @@ (define_insn "sse5_rotr<mode>3"
   return \"prot<ssevecsize>\t{%3, %1, %0|%0, %1, %3}\";
 }
   [(set_attr "type" "sseishft")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_expand "vrotr<mode>3"
@@ -11082,6 +11327,8 @@ (define_insn "sse5_vrotl<mode>3"
   "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 3, true, 1, false)"
   "prot<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseishft")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_extra" "2")
    (set_attr "mode" "TI")])
 
 ;; SSE5 packed shift instructions.
@@ -11135,6 +11382,8 @@ (define_insn "sse5_ashl<mode>3"
   "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 3, true, 1, false)"
   "psha<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseishft")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_extra" "2")
    (set_attr "mode" "TI")])
 
 (define_insn "sse5_lshl<mode>3"
@@ -11152,6 +11401,8 @@ (define_insn "sse5_lshl<mode>3"
   "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 3, true, 1, false)"
   "pshl<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseishft")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_extra" "2")
    (set_attr "mode" "TI")])
 
 ;; SSE2 doesn't have some shift varients, so define versions for SSE5
@@ -11265,7 +11516,6 @@ (define_insn "sse5_frcz<mode>2"
   "TARGET_SSE5"
   "frcz<ssemodesuffixf4>\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt1")
-   (set_attr "prefix_extra" "1")
    (set_attr "mode" "<MODE>")])
 
 ;; scalar insns
@@ -11280,7 +11530,6 @@ (define_insn "sse5_vmfrcz<mode>2"
   "TARGET_SSE5"
   "frcz<ssemodesuffixf2s>\t{%2, %0|%0, %2}"
   [(set_attr "type" "ssecvt1")
-   (set_attr "prefix_extra" "1")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "sse5_cvtph2ps"
@@ -11329,6 +11578,10 @@ (define_insn "*sse5_vmmaskcmp<mode>3"
   "TARGET_SSE5"
   "com%Y1<ssemodesuffixf2s>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "sse4arg")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_rep" "0")
+   (set_attr "prefix_extra" "2")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "<ssescalarmode>")])
 
 ;; We don't have a comparison operator that always returns true/false, so
@@ -11369,6 +11622,10 @@ (define_insn "sse5_com_tf<mode>3"
   return ret;
 }
   [(set_attr "type" "ssecmp")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_rep" "0")
+   (set_attr "prefix_extra" "2")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "sse5_maskcmp<mode>3"
@@ -11379,6 +11636,10 @@ (define_insn "sse5_maskcmp<mode>3"
   "TARGET_SSE5"
   "com%Y1<ssemodesuffixf4>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "ssecmp")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_rep" "0")
+   (set_attr "prefix_extra" "2")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "<MODE>")])
 
 (define_insn "sse5_maskcmp<mode>3"
@@ -11389,6 +11650,10 @@ (define_insn "sse5_maskcmp<mode>3"
   "TARGET_SSE5"
   "pcom%Y1<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "sse4arg")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_rep" "0")
+   (set_attr "prefix_extra" "2")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_insn "sse5_maskcmp_uns<mode>3"
@@ -11399,6 +11664,10 @@ (define_insn "sse5_maskcmp_uns<mode>3"
   "TARGET_SSE5"
   "pcom%Y1u<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "ssecmp")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_rep" "0")
+   (set_attr "prefix_extra" "2")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 ;; Version of pcom*u* that is called from the intrinsics that allows pcomequ*
@@ -11414,6 +11683,9 @@ (define_insn "sse5_maskcmp_uns2<mode>3"
   "TARGET_SSE5"
   "pcom%Y1u<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "ssecmp")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_extra" "2")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 ;; Pcomtrue and pcomfalse support.  These are useless instructions, but are
@@ -11432,6 +11704,9 @@ (define_insn "sse5_pcom_tf<mode>3"
 	  : "pcomfalse<ssevecsize>\t{%2, %1, %0|%0, %1, %2}");
 }
   [(set_attr "type" "ssecmp")
+   (set_attr "prefix_data16" "0")
+   (set_attr "prefix_extra" "2")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_insn "*avx_aesenc"
@@ -11442,6 +11717,7 @@ (define_insn "*avx_aesenc"
   "TARGET_AES && TARGET_AVX"
   "vaesenc\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog1")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -11464,6 +11740,7 @@ (define_insn "*avx_aesenclast"
   "TARGET_AES && TARGET_AVX"
   "vaesenclast\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog1")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -11486,6 +11763,7 @@ (define_insn "*avx_aesdec"
   "TARGET_AES && TARGET_AVX"
   "vaesdec\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog1")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -11508,6 +11786,7 @@ (define_insn "*avx_aesdeclast"
   "TARGET_AES && TARGET_AVX"
   "vaesdeclast\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog1")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -11542,6 +11821,7 @@ (define_insn "aeskeygenassist"
   "%vaeskeygenassist\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "maybe_vex")
    (set_attr "mode" "TI")])
 
@@ -11554,6 +11834,8 @@ (define_insn "*vpclmulqdq"
   "TARGET_PCLMUL && TARGET_AVX"
   "vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "sselog1")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "TI")])
 
@@ -11567,6 +11849,7 @@ (define_insn "pclmulqdq"
   "pclmulqdq\t{%3, %2, %0|%0, %2, %3}"
   [(set_attr "type" "sselog1")
    (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "mode" "TI")])
 
 (define_expand "avx_vzeroall"
@@ -11597,6 +11880,7 @@ (define_insn "*avx_vzeroall"
   "TARGET_AVX"
   "vzeroall"
   [(set_attr "type" "sse")
+   (set_attr "modrm" "0")
    (set_attr "memory" "none")
    (set_attr "prefix" "vex")
    (set_attr "mode" "OI")])
@@ -11615,6 +11899,7 @@ (define_insn "avx_vzeroupper"
   "TARGET_AVX && !TARGET_64BIT"
   "vzeroupper"
   [(set_attr "type" "sse")
+   (set_attr "modrm" "0")
    (set_attr "memory" "none")
    (set_attr "prefix" "vex")
    (set_attr "mode" "OI")])
@@ -11640,6 +11925,7 @@ (define_insn "avx_vzeroupper_rex64"
   "TARGET_AVX && TARGET_64BIT"
   "vzeroupper"
   [(set_attr "type" "sse")
+   (set_attr "modrm" "0")
    (set_attr "memory" "none")
    (set_attr "prefix" "vex")
    (set_attr "mode" "OI")])
@@ -11653,6 +11939,8 @@ (define_insn "avx_vpermil<mode>"
   "TARGET_AVX"
   "vpermilp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<MODE>")])
 
@@ -11665,6 +11953,7 @@ (define_insn "avx_vpermilvar<mode>3"
   "TARGET_AVX"
   "vpermilp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<MODE>")])
 
@@ -11678,6 +11967,8 @@ (define_insn "avx_vperm2f128<mode>3"
   "TARGET_AVX"
   "vperm2f128\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
 
@@ -11693,6 +11984,7 @@ (define_insn "avx_vbroadcasts<avxmodesuf
   "TARGET_AVX"
   "vbroadcasts<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssemov")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<avxscalarmode>")])
 
@@ -11716,6 +12008,7 @@ (define_insn "avx_vbroadcastss256"
   "TARGET_AVX"
   "vbroadcastss\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssemov")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "SF")])
 
@@ -11727,6 +12020,7 @@ (define_insn "avx_vbroadcastf128_p<avxmo
   "TARGET_AVX"
   "vbroadcastf128\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssemov")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V4SF")])
 
@@ -11763,6 +12057,8 @@ (define_insn "vec_set_lo_<mode>"
   "TARGET_AVX"
   "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
 
@@ -11776,6 +12072,8 @@ (define_insn "vec_set_hi_<mode>"
   "TARGET_AVX"
   "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
 
@@ -11790,6 +12088,8 @@ (define_insn "vec_set_lo_<mode>"
   "TARGET_AVX"
   "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
 
@@ -11804,6 +12104,8 @@ (define_insn "vec_set_hi_<mode>"
   "TARGET_AVX"
   "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
 
@@ -11820,6 +12122,8 @@ (define_insn "vec_set_lo_v16hi"
   "TARGET_AVX"
   "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
 
@@ -11836,6 +12140,8 @@ (define_insn "vec_set_hi_v16hi"
   "TARGET_AVX"
   "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
 
@@ -11856,6 +12162,8 @@ (define_insn "vec_set_lo_v32qi"
   "TARGET_AVX"
   "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
 
@@ -11876,6 +12184,8 @@ (define_insn "vec_set_hi_v32qi"
   "TARGET_AVX"
   "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
   [(set_attr "type" "sselog")
+   (set_attr "prefix_extra" "1")
+   (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V8SF")])
 
@@ -11889,6 +12199,7 @@ (define_insn "avx_maskloadp<avxmodesuffi
   "TARGET_AVX"
   "vmaskmovp<avxmodesuffixf2c>\t{%1, %2, %0|%0, %2, %1}"
   [(set_attr "type" "sselog1")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<MODE>")])
 
@@ -11902,6 +12213,7 @@ (define_insn "avx_maskstorep<avxmodesuff
   "TARGET_AVX"
   "vmaskmovp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sselog1")
+   (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<MODE>")])
 
@@ -12012,5 +12324,7 @@ (define_insn "*vec_concat<mode>_avx"
     }
 }
   [(set_attr "type" "sselog,ssemov")
+   (set_attr "prefix_extra" "1,*")
+   (set_attr "length_immediate" "1,*")
    (set_attr "prefix" "vex")
    (set_attr "mode" "<avxvecmode>")])


	Jakub


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]